forked from github/verilator
52912c6329
- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
30 lines
593 B
Verilog
30 lines
593 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire [7:0] bitout;
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reg [7:0] allbits;
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reg [7:0] onebit;
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reg [8:0] onebitbad; // Wrongly sized
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sub sub [7:0] (allbits, onebitbad, bitout);
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// This is ok.
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wire [9:8] b;
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wire [1:0] c;
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sub sub2 [9:8] (allbits,b,c);
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endmodule
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module sub (input [7:0] allbits, input onebit, output bitout);
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wire bitout = onebit ^ (^ allbits);
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endmodule
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