forked from github/verilator
e5b1fdf668
Squashed commit of the following: commit c1eeda7d472fc14a0ffd5c1712ae7f7c614073a1 Author: Iztok Jeras <iztok.jeras@gmail.com> Date: Tue Mar 20 16:39:44 2012 +0100 - fixed assignment operator in t_array_packed_write_read.v from = to <= - added tests for enumerations (existing tests do not use methods like next(), num(), ...) - added t_sv_bus_mux_demux test, with packed arrays, structures and unions
54 lines
1.1 KiB
Verilog
54 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Iztok Jeras.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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parameter SIZE = 8;
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integer cnt = 0;
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logic [SIZE-1:0] vld_for;
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logic vld_if = 1'b0;
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logic vld_else = 1'b0;
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genvar i;
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// event counter
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always @ (posedge clk) begin
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cnt <= cnt + 1;
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end
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// finish report
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always @ (posedge clk)
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if (cnt==SIZE) begin : if_cnt_finish
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$write("*-* All Finished *-*\n");
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$finish;
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end : if_cnt_finish_bad
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generate
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for (i=0; i<SIZE; i=i+1) begin : generate_for
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always @ (posedge clk)
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if (cnt == i) vld_for[i] <= 1'b1;
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end : generate_for_bad
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endgenerate
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generate
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if (SIZE>0) begin : generate_if_if
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always @ (posedge clk)
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vld_if <= 1'b1;
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end : generate_if_if_bad
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else begin : generate_if_else
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always @ (posedge clk)
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vld_else <= 1'b1;
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end : generate_if_else_bad
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endgenerate
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endmodule : t_bad
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