verilator/test_regress/t/t_hierarchy_identifier_bad.pl
Wilson Snyder e5b1fdf668 Tests: Added additional SystemVerilog tests.
Squashed commit of the following:

commit c1eeda7d472fc14a0ffd5c1712ae7f7c614073a1
Author: Iztok Jeras <iztok.jeras@gmail.com>
Date:   Tue Mar 20 16:39:44 2012 +0100

- fixed assignment operator in t_array_packed_write_read.v from = to <=
- added tests for enumerations (existing tests do not use methods like
next(), num(), ...)
- added t_sv_bus_mux_demux test, with packed arrays, structures and unions
2012-03-20 19:28:35 -04:00

25 lines
1.1 KiB
Perl
Executable File

#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
q{%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:\d+: End label 'if_cnt_finish_bad' does not match begin label 'if_cnt_finish'
%Warning-ENDLABEL: Use .*
%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:\d+: End label 'generate_for_bad' does not match begin label 'generate_for'
%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:\d+: End label 'generate_if_if_bad' does not match begin label 'generate_if_if'
%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:\d+: End label 'generate_if_else_bad' does not match begin label 'generate_if_else'
%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:\d+: End label 't_bad' does not match begin label 't'
%Error: Exiting due to.*},
);
ok(1);
1;