forked from github/verilator
18 lines
331 B
Verilog
18 lines
331 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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// See bug408
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module top
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(
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output logic [1:0] q,
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input logic [1:0] d,
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input logic clk
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);
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genvar i;
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assign q[i] = d[i];
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endmodule
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