forked from github/verilator
20 lines
352 B
Verilog
20 lines
352 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2011 by Wilson Snyder.
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module t (/*AUTOARG*/);
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initial begin
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func(0, 1'b1);
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end
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function automatic int func
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(
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input int a,
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output bit b );
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return 0;
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endfunction
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endmodule
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