forked from github/verilator
52912c6329
- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
33 lines
712 B
Verilog
33 lines
712 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2006 by Wilson Snyder.
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module t (clk, Rand);
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input clk;
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output reg [31:0] Rand;
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`ifdef verilator
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`systemc_interface
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unsigned int QxRandTbl (unsigned int tbl, unsigned int idx) { return 0xfeed0fad; }
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`verilog
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`endif
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function [31:0] QxRand32;
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/* verilator public */
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input [7:0] tbl;
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input [7:0] idx;
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begin
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`ifdef verilator
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QxRand32 = $c ("QxRandTbl(",tbl,",",idx,")");
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`else
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QxRand32 = 32'hfeed0fad;
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`endif
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end
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endfunction
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always @(posedge clk) begin
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Rand <= #1 QxRand32 (8'h0, 8'h7);
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end
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endmodule
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