forked from github/verilator
49 lines
1.2 KiB
Verilog
49 lines
1.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t;
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// Speced ignored: system calls. I think this is nasty, so we error instead.
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// Speced Illegal: inout/output/ref not allowed
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localparam B1 = f_bad_output(1,2);
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function integer f_bad_output(input [31:0] a, output [31:0] o);
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f_bad_output = 0;
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endfunction
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// Speced Illegal: void
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// Speced Illegal: dotted
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localparam EIGHT = 8;
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localparam B2 = f_bad_dotted(2);
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function integer f_bad_dotted(input [31:0] a);
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f_bad_dotted = t.EIGHT;
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endfunction
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// Speced Illegal: ref to non-local var
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integer modvar;
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localparam B3 = f_bad_nonparam(3);
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function integer f_bad_nonparam(input [31:0] a);
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f_bad_nonparam = modvar;
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endfunction
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// Speced Illegal: needs constant function itself
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// Our own - infinite loop
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localparam B4 = f_bad_infinite(3);
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function integer f_bad_infinite(input [31:0] a);
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while (1) begin
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f_bad_infinite = 0;
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end
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endfunction
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// Our own - stop
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localparam BSTOP = f_bad_stop(3);
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function integer f_bad_stop(input [31:0] a);
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$stop;
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endfunction
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endmodule
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