forked from github/verilator
88 lines
1.9 KiB
Verilog
88 lines
1.9 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t;
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localparam P4 = f_add(P3,1);
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localparam P8 = f_add2(P3,P3,f_add(1,1));
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localparam P5 = f_while(7);
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localparam P16 = f_for(P4);
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localparam P18 = f_case(P4);
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localparam P6 = f_return(P4);
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localparam P3 = 3;
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initial begin
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`ifdef TEST_VERBOSE
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$display("P5=%0d P8=%0d P16=%0d P18=%0d",P5,P8,P16,P18);
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`endif
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if (P3 !== 3) $stop;
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if (P4 !== 4) $stop;
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if (P5 !== 5) $stop;
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if (P6 !== 6) $stop;
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if (P8 !== 8) $stop;
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if (P16 !== 16) $stop;
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if (P18 !== 18) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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function integer f_add(input [31:0] a, input [31:0] b);
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f_add = a+b;
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endfunction
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// Speced ok: function called from function
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function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c);
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f_add2 = f_add(a,b)+c;
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endfunction
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// Speced ok: local variables
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function integer f_for(input [31:0] a);
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integer i;
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integer times;
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begin
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times = 1;
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for (i=0; i<a; i=i+1) times = times*2;
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f_for = times;
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end
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endfunction
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function integer f_while(input [31:0] a);
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integer i;
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begin
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i=0;
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begin : named
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f_while = 1;
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end : named
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while (i<=a) begin
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if (i[0]) f_while = f_while + 1;
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i = i + 1;
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end
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end
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endfunction
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// Speced ok: local variables
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function integer f_case(input [31:0] a);
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case(a)
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32'd1: f_case = 1;
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32'd0, 32'd4: f_case = 18;
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32'd1234: begin $display("never get here"); $stop; end
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default: f_case = 99;
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endcase
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endfunction
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function integer f_return(input [31:0] a);
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integer out = 2;
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while (1) begin
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out = out+1;
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if (a>1) break;
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end
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while (1) begin
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out = out+1;
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if (a>1) return 2+out;
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end
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f_return = 0;
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endfunction
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endmodule
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