forked from github/verilator
28 lines
877 B
Perl
Executable File
28 lines
877 B
Perl
Executable File
#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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top_filename("t/t_flag_wfatal.v");
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$Self->{vlt} or $Self->skip("Verilator only test");
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compile (
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v_flags2 => ["--lint-only -Wno-fatal"],
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fails=>0,
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verilator_make_gcc => 0,
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make_top_shell => 0,
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make_main => 0,
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expect=>
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q{%Warning-WIDTH: t/t_flag_wfatal.v:\d+: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS.s CONST '6'h2e' generates 6 bits.
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%Warning-WIDTH: Use .* and lint_on around source to disable this message.
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},
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);
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ok(1);
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1;
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