forked from github/verilator
30 lines
511 B
Verilog
30 lines
511 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module a;
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a2 a2 (.tmp(1'b0));
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initial begin
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$write("Bad top modules\n");
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$stop;
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end
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endmodule
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module a2 (input tmp);
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l3 l3 (.tmp(tmp));
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endmodule
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module b;
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l3 l3 (.tmp(1'b1));
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endmodule
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module l3 (input tmp);
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initial begin
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if (tmp) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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