forked from github/verilator
42 lines
877 B
Verilog
42 lines
877 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2009 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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module t;
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wire [39:0] out;
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sub a(.value(out));
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import "DPI-C" context function void poke_value(input int i);
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initial begin
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poke_value(32'hdeadbeef);
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if (out !== 40'hdeadbeef) begin
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$display("[%0t] %%Error: t_dpi_qw: failed", $time);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub(value);
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parameter WIDTH = 40;
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output [WIDTH-1:0] value;
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reg [WIDTH-1:0] value;
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task set_value(input bit [WIDTH-1:0] v);
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value = v;
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endtask
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export "DPI-C" task set_value;
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endmodule
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