forked from github/verilator
53 lines
1.2 KiB
Verilog
53 lines
1.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2009 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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module t ();
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sub a (.inst(1));
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sub b (.inst(2));
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initial begin
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a.test1;
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b.test1;
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a.test2;
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b.test2;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub (input integer inst);
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import "DPI-C" context function int dpic_line();
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import "DPI-C" context function int dpic_save(int value);
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import "DPI-C" context function int dpic_restore();
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int result;
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task test1;
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// Check line numbering
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`ifndef verilator // Not all sims support SV2009 `__LINE__, and some that do fail the specific-line test
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result = dpic_line(); if (!result) $stop;
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`else
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result = dpic_line(); if (result !== `__LINE__) $stop;
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//
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result = dpic_line(); if (result !== `__LINE__) $stop;
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`endif
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// Check save-restore
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result = dpic_save(23+inst);
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if (result==0) $stop;
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endtask
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task test2;
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if (dpic_restore() != 23+inst) $stop;
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endtask
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endmodule
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