forked from github/verilator
18 lines
577 B
Verilog
18 lines
577 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005-2007 by Wilson Snyder.
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module t (/*AUTOARG*/);
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parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; // One to many digits
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parameter [200:0] SMALLH = 8'habc; // One to many digits
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parameter [200:0] SMALLO = 6'o1234; // One to many digits
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parameter [200:0] SMALLB = 3'b1111; // One to many digits
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// We'll allow this though; no reason to be cruel
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parameter [200:0] OKH = 8'h000000001;
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endmodule
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