forked from github/verilator
30 lines
606 B
Verilog
30 lines
606 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2011 by Wilson Snyder.
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module t;
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typedef logic [3:0] mc_t;
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typedef mc_t tocast_t;
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mc_t o;
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logic [15:0] allones = 16'hffff;
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initial begin
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if (4'shf > 4'sh0) $stop;
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if (signed'(4'hf) > 4'sh0) $stop;
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if (4'hf < 4'h0) $stop;
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if (unsigned'(4'shf) < 4'h0) $stop;
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if (4'(allones) !== 4'hf) $stop;
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o = tocast_t'(4'b1);
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if (o != 4'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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