forked from github/verilator
44 lines
983 B
Verilog
44 lines
983 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2006 by Wilson Snyder.
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`include "verilated.v"
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [63:0] crc;
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`verilator_file_descriptor fd;
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t_case_write2_tasks tasks ();
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integer cyc; initial cyc=0;
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always @ (posedge clk) begin
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$fwrite(fd, "[%0d] crc=%x ", cyc, crc);
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tasks.big_case(fd, crc[31:0]);
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$fwrite(fd, "\n");
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end
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always @ (posedge clk) begin
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//$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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if (cyc==1) begin
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crc <= 64'h00000000_00000097;
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$write("Open obj_dir/t_case_write2/t_case_write2_logger.log\n");
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fd = $fopen("obj_dir/t_case_write2/t_case_write2_logger.log", "w");
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end
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if (cyc==90) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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