forked from github/verilator
43 lines
922 B
Verilog
43 lines
922 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// A test case for struct signal bit selection.
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//
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// This test is to check that bit selection of multi-dimensional signal inside
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// of a packed struct works. Currently +: and -: blow up with packed structs.
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//
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// This file ONLY is placed into the Public Domain, for any use, without
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// warranty, 2013 by Jie Xu.
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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typedef struct packed {
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logic [15:0] channel;
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logic [15:0] others;
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} buss_t;
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buss_t b;
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reg [7:0] a;
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reg [7:0] c;
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reg [7:0] d;
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initial begin
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b = {16'h8765,16'h4321};
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a = b[19:12]; // This works
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c = b[8+:8]; // This fails
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d = b[11-:8]; // This fails
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if ((a == 8'h54) && (c == 8'h43) && (d == 8'h32)) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$stop;
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end
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end
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endmodule
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