forked from github/verilator
13 lines
730 B
Plaintext
13 lines
730 B
Plaintext
%Warning-CLKDATA: t/t_clocker.v:45:17: Clock is assigned to part of data signal 'res8'
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45 | assign res8 = {clk_3, 1'b0, clk_4};
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| ^
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... For warning description see https://verilator.org/warn/CLKDATA?v=latest
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... Use "/* verilator lint_off CLKDATA */" and lint_on around source to disable this message.
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%Warning-CLKDATA: t/t_clocker.v:46:17: Clock is assigned to part of data signal 'res16'
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46 | assign res16 = {count, clk_3, clk_1, clk_4};
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| ^
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%Warning-CLKDATA: t/t_clocker.v:57:14: Clock used as data (on rhs of assignment) in sequential block 'clk'
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57 | res <= clk_final;
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| ^~~~~~~~~
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%Error: Exiting due to
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