forked from github/verilator
2c813488f4
This commit adds the '--simbenchmark' option to the regression test compile command. The option is not intended as a fully-fledged benchmarking infrastructure, but rather a utility for easily generating cycle- and execution time information when executing a verilated test. As an example use case, the included test file shows how optimization level is varied across three different builds+simulations, with the statistics for each run output to the same file in the output directory. Future work: - 'sim_time' in the generated top-level main file should be a parameter. - Given the above, the test execution script from verilog-sim-benchmark can be integrated to generate better estimates of cycles/second through varying 'sim_time' over multiple executions. |
||
|---|---|---|
| .. | ||
| t | ||
| .gdbinit | ||
| .gitignore | ||
| CMakeLists.txt | ||
| driver.pl | ||
| input.vc | ||
| input.xsim.vc | ||
| Makefile | ||
| Makefile_obj | ||