Add TRACE_THREADS to CMake (#2934)

docs/CONTRIBUTORS

@@ -38,6 +38,7 @@ Jean Berniolles
 Jeremy Bennett
 John Coiner
 John Demme
+Jonathan Drolet
 Josh Redford
 Julien Margetts
 Kaleb Barrett

docs/guide/verilating.rst

@@ -360,7 +360,8 @@ Verilate in CMake
      verilate(target SOURCES source ... [TOP_MODULE top] [PREFIX name]
               [TRACE] [TRACE_FST] [SYSTEMC] [COVERAGE]
               [INCLUDE_DIRS dir ...] [OPT_SLOW ...] [OPT_FAST ...]
-              [OPT_GLOBAL ..] [DIRECTORY dir] [VERILATOR_ARGS ...])
+              [OPT_GLOBAL ..] [DIRECTORY dir] [THREADS num]
+              [TRACE_THREADS num] [VERILATOR_ARGS ...])
 
 Lowercase and ... should be replaced with arguments, the uppercase parts
 delimit the arguments and can be passed in any order, or left out entirely
@@ -429,6 +430,15 @@ SystemC include directories and link to the SystemC libraries.
    the SystemC library. This can be specified using the SYSTEMC_CXX_FLAGS
    environment variable.
 
+.. describe:: THREADS
+
+   Optional. Generated a multi-threaded model, same as "--threads".
+
+.. describe:: TRACE_THREADS
+
+   Optional. Generated multi-threaded trace dumping, same as
+   "--trace-threads".
+
 .. describe:: TOP_MODULE
 
    Optional. Sets the name of the top module. Defaults to the name of the

src/V3EmitCMake.cpp

@@ -113,6 +113,8 @@ class CMakeEmitter final {
         cmake_set_raw(*of, name + "_COVERAGE", v3Global.opt.coverage() ? "1" : "0");
         *of << "# Threaded output mode?  0/1/N threads (from --threads)\n";
         cmake_set_raw(*of, name + "_THREADS", cvtToStr(v3Global.opt.threads()));
+        *of << "# Threaded tracing output mode?  0/1/N threads (from --trace-threads)\n";
+        cmake_set_raw(*of, name + "_TRACE_THREADS", cvtToStr(v3Global.opt.traceThreads()));
         *of << "# VCD Tracing output mode?  0/1 (from --trace)\n";
         cmake_set_raw(*of, name + "_TRACE_VCD",
                       (v3Global.opt.trace() && (v3Global.opt.traceFormat() == TraceFormat::VCD))

test_regress/CMakeLists.txt

@@ -52,9 +52,10 @@ string(REGEX REPLACE "(^|;)--" "\\1-"
 
 getarg(TEST_VERILATOR_ARGS_NORM "-prefix" TEST_PREFIX)
 getarg(TEST_VERILATOR_ARGS_NORM "-threads" TEST_THREADS)
+getarg(TEST_VERILATOR_ARGS_NORM "-trace-threads" TEST_TRACE_THREADS)
 
 # Strip unwanted args with 1 parameter
-string(REGEX REPLACE "(^|;)--?(Mdir|make|prefix|threads);[^;]*" ""
+string(REGEX REPLACE "(^|;)--?(Mdir|make|prefix|threads|trace-threads);[^;]*" ""
        TEST_VERILATOR_ARGS
        "${TEST_VERILATOR_ARGS}")
 # Strip unwanted args
@@ -81,6 +82,9 @@ endif()
 if(TEST_THREADS)
   list(APPEND verilate_ARGS THREADS ${TEST_THREADS})
 endif()
+if(TEST_TRACE_THREADS)
+  list(APPEND verilate_ARGS TRACE_THREADS ${TEST_TRACE_THREADS})
+endif()
 if(TEST_SYSTEMC)
   list(APPEND verilate_ARGS SYSTEMC)
 endif()

test_regress/t/t_trace_fst_cmake.pl

@@ -0,0 +1,27 @@
+#!/usr/bin/env perl
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+
+scenarios(vlt_all => 1);
+
+compile(
+    v_flags2 => ["--trace-fst"],
+    verilator_make_gmake => 0,
+    verilator_make_cmake => 1,
+);
+
+execute(
+    check_finished => 1,
+);
+
+fst_identical($Self->trace_filename, $Self->{golden_filename});
+
+ok(1);
+1;

test_regress/t/t_trace_fst_cmake.v

@@ -0,0 +1,99 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Outputs
+   state,
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   int   cyc;
+   reg   rstn;
+   output [4:0] state;
+
+   parameter real  fst_gparam_real = 1.23;
+   localparam real fst_lparam_real = 4.56;
+   real            fst_real = 1.23;
+   integer         fst_integer;
+   bit             fst_bit;
+   logic           fst_logic;
+   int             fst_int;
+   shortint        fst_shortint;
+   longint         fst_longint;
+   byte            fst_byte;
+
+   parameter       fst_parameter = 123;
+   localparam      fst_lparam = 456;
+   supply0         fst_supply0;
+   supply1         fst_supply1;
+   tri0            fst_tri0;
+   tri1            fst_tri1;
+   tri             fst_tri;
+   wire            fst_wire;
+
+   Test test (/*AUTOINST*/
+              // Outputs
+              .state                    (state[4:0]),
+              // Inputs
+              .clk                      (clk),
+              .rstn                     (rstn));
+
+   // Test loop
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc==0) begin
+         // Setup
+         rstn <= ~'1;
+      end
+      else if (cyc<10) begin
+         rstn <= ~'1;
+      end
+      else if (cyc<90) begin
+         rstn <= ~'0;
+      end
+      else if (cyc==99) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
+
+
+module Test (
+          input              clk,
+          input              rstn,
+          output logic [4:0] state
+          );
+
+   logic [4:0]               state_w;
+   logic [4:0]               state_array [3];
+   assign state = state_array[0];
+
+   always_comb begin
+      state_w[4] = state_array[2][0];
+      state_w[3] = state_array[2][4];
+      state_w[2] = state_array[2][3] ^ state_array[2][0];
+      state_w[1] = state_array[2][2];
+      state_w[0] = state_array[2][1];
+   end
+
+   always_ff @(posedge clk or negedge rstn) begin
+      if (!rstn) begin
+         for (int i = 0; i < 3; i++)
+           state_array[i] <= 'b1;
+      end
+      else begin
+         for (int i = 0; i < 2; i++)
+           state_array[i] <= state_array[i+1];
+         state_array[2] <= state_w;
+      end
+   end
+
+endmodule

verilator-config.cmake.in

@@ -83,6 +83,12 @@ define_property(TARGET
   FULL_DOCS "Verilator multithreading enabled"
 )
 
+define_property(TARGET
+  PROPERTY VERILATOR_TRACE_THREADED
+  BRIEF_DOCS "Verilator multithread tracing enabled"
+  FULL_DOCS "Verilator multithread tracing enabled"
+)
+
 define_property(TARGET
   PROPERTY VERILATOR_COVERAGE
   BRIEF_DOCS "Verilator coverage enabled"
@@ -115,7 +121,7 @@ define_property(TARGET
 
 function(verilate TARGET)
   cmake_parse_arguments(VERILATE "COVERAGE;TRACE;TRACE_FST;SYSTEMC"
-                                 "PREFIX;TOP_MODULE;THREADS;DIRECTORY"
+                                 "PREFIX;TOP_MODULE;THREADS;TRACE_THREADS;DIRECTORY"
                                  "SOURCES;VERILATOR_ARGS;INCLUDE_DIRS;OPT_SLOW;OPT_FAST;OPT_GLOBAL"
                                  ${ARGN})
   if (NOT VERILATE_SOURCES)
@@ -136,6 +142,10 @@ function(verilate TARGET)
     list(APPEND VERILATOR_ARGS --threads ${VERILATE_THREADS})
   endif()
 
+  if (VERILATE_TRACE_THREADS)
+    list(APPEND VERILATOR_ARGS --trace-threads ${VERILATE_TRACE_THREADS})
+  endif()
+
   if (VERILATE_COVERAGE)
     list(APPEND VERILATOR_ARGS --coverage)
   endif()
@@ -240,6 +250,11 @@ function(verilate TARGET)
     set_property(TARGET ${TARGET} PROPERTY VERILATOR_THREADED ON)
   endif()
 
+  if (${VERILATE_PREFIX}_TRACE_THREADS)
+    # If any verilate() call specifies TRACE_THREADS, define VL_TRACE_THREADED in the final build
+    set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_THREADED ON)
+  endif()
+
   if (${VERILATE_PREFIX}_COVERAGE)
     # If any verilate() call specifies COVERAGE, define VM_COVERAGE in the final build
     set_property(TARGET ${TARGET} PROPERTY VERILATOR_COVERAGE ON)
@@ -296,6 +311,7 @@ function(verilate TARGET)
     VM_COVERAGE=$<BOOL:$<TARGET_PROPERTY:VERILATOR_COVERAGE>>
     VM_SC=$<BOOL:$<TARGET_PROPERTY:VERILATOR_SYSTEMC>>
     $<$<BOOL:$<TARGET_PROPERTY:VERILATOR_THREADED>>:VL_THREADED>
+    $<$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE_THREADED>>:VL_TRACE_THREADED>
     VM_TRACE=$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE>>
     VM_TRACE_VCD=$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE_VCD>>
     VM_TRACE_FST=$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE_FST>>