forked from github/verilator
1e938d0e90
Fix preprocessor preservation of newlines across macro substitutions. Fix preprocessor stringification of nested macros. Fix preprocessor whitespace on define arguments
89 lines
1.4 KiB
Plaintext
89 lines
1.4 KiB
Plaintext
`line 1 "t/t_preproc_psl.v" 1
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`line 7 "t/t_preproc_psl.v" 0
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/*verilator metacomment preserved*/
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`line 9 "t/t_preproc_psl.v" 0
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/*verilator metacomment also_preserved*/
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`line 11 "t/t_preproc_psl.v" 0
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Hello in t_preproc_psl.v
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`line 17 "t/t_preproc_psl.v" 0
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psl default clock = (posedge clk);
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psl fails1: cover {cyc==10};
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psl assert always cyc!=10;
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psl assert always cyc==3 -> mask==8'h2;
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psl failsx: cover {cyc==3 && mask==8'h1};
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psl fails2:
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cover {
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cyc==3 && mask==8'h9};
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fails3: always assert {
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cyc==3 && mask==8'h10 };
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29
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`line 31 "t/t_preproc_psl.v" 0
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psl
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`line 35 "t/t_preproc_psl.v" 0
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fails_ml:
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assert always
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cyc==3 -> mask==8'h21;
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psl
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fails_mlalso: assert always cyc==3 -> mask==8'h21;
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41
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`line 43 "t/t_preproc_psl.v" 0
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psl assert never (cyc==1 && reset_l);
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`line 45 "t/t_preproc_psl.v" 0
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psl fails3: assert always
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psl cyc==3 -> mask==8'h21;
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`line 50 "t/t_preproc_psl.v" 0
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psl assert always
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psl {[*]; cyc==3;
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psl cyc==4; cyc==6};
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`line 57 "t/t_preproc_psl.v" 0
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`line 62 "t/t_preproc_psl.v" 0
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psl assert always cyc!=10;
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`line 65 "t/t_preproc_psl.v" 0
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`psl
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psl assert always sig!=90;
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`verilog
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`line 72 "t/t_preproc_psl.v" 0
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72
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`line 74 "t/t_preproc_psl.v" 2
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