Wilson Snyder
1e938d0e90
Update preprocessor to match next Verilog-Perl version.
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Fix preprocessor preservation of newlines across macro substitutions.
Fix preprocessor stringification of nested macros.
Fix preprocessor whitespace on define arguments
2010-07-10 18:30:16 -04:00
Wilson Snyder
a16477d84f
Fix SystemVerilog parameterized defines and whitespace
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git-svn-id: file://localhost/svn/verilator/trunk/verilator@1013 77ca24e4-aefa-0310-84f0-b9a241c72d87
2008-03-27 13:21:49 +00:00
Wilson Snyder
79d305f3e8
Match Verilog-Perl: Remove preprocessor adding newlines before `line.
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git-svn-id: file://localhost/svn/verilator/trunk/verilator@948 77ca24e4-aefa-0310-84f0-b9a241c72d87
2007-07-30 15:00:21 +00:00
Wilson Snyder
ce10dbd11c
Version bump
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git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
2006-08-26 11:35:28 +00:00
