forked from github/verilator
86 lines
3.8 KiB
XML
86 lines
3.8 KiB
XML
<?xml version="1.0" ?>
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<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
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<verilator_xml>
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<files>
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<file id="a" filename="<built-in>" language="1800-2017"/>
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<file id="b" filename="<command-line>" language="1800-2017"/>
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<file id="c" filename="input.vc" language="1800-2017"/>
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<file id="d" filename="t/t_xml_first.v" language="1800-2017"/>
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</files>
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<module_files>
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<file id="d" filename="t/t_xml_first.v" language="1800-2017"/>
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</module_files>
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<cells>
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<cell fl="d6" name="t" submodname="t" hier="t">
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<cell fl="d19" name="cell1" submodname="mod1__W4" hier="t.cell1"/>
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<cell fl="d24" name="cell2" submodname="mod2" hier="t.cell2"/>
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</cell>
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</cells>
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<netlist>
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<module fl="d6" name="t" origName="t" topModule="1">
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<var fl="d12" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="d13" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="d14" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<var fl="d16" name="between" dtype_id="2" vartype="logic" origName="between"/>
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<instance fl="d19" name="cell1" defName="mod1__W4" origName="cell1">
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<port fl="d19" name="q" direction="out" portIndex="1">
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<varref fl="d19" name="between" dtype_id="2"/>
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</port>
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<port fl="d20" name="clk" direction="in" portIndex="2">
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<varref fl="d20" name="clk" dtype_id="1"/>
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</port>
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<port fl="d21" name="d" direction="in" portIndex="3">
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<varref fl="d21" name="d" dtype_id="2"/>
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</port>
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</instance>
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<instance fl="d24" name="cell2" defName="mod2" origName="cell2">
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<port fl="d24" name="d" direction="in" portIndex="1">
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<varref fl="d24" name="between" dtype_id="2"/>
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</port>
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<port fl="d25" name="q" direction="out" portIndex="2">
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<varref fl="d25" name="q" dtype_id="2"/>
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</port>
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<port fl="d26" name="clk" direction="in" portIndex="3">
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<varref fl="d26" name="clk" dtype_id="1"/>
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</port>
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</instance>
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</module>
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<module fl="d30" name="mod1__W4" origName="mod1">
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<var fl="d31" name="WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">
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<const fl="d18" name="32'sh4" dtype_id="3"/>
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</var>
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<var fl="d33" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="d34" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="d35" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<var fl="d38" name="IGNORED" dtype_id="3" vartype="logic" origName="IGNORED" localparam="true">
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<const fl="d38" name="32'sh1" dtype_id="3"/>
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</var>
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<always fl="d40">
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<sentree fl="d40">
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<senitem fl="d40" edgeType="POS">
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<varref fl="d40" name="clk" dtype_id="1"/>
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</senitem>
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</sentree>
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<assigndly fl="d41" dtype_id="2">
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<varref fl="d41" name="d" dtype_id="2"/>
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<varref fl="d41" name="q" dtype_id="2"/>
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</assigndly>
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</always>
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</module>
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<module fl="d45" name="mod2" origName="mod2">
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<var fl="d47" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="d48" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="d49" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<contassign fl="d52" dtype_id="2">
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<varref fl="d52" name="d" dtype_id="2"/>
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<varref fl="d52" name="q" dtype_id="2"/>
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</contassign>
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</module>
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<typetable fl="a0">
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<basicdtype fl="d47" id="1" name="logic"/>
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<basicdtype fl="d13" id="2" name="logic" left="3" right="0"/>
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<basicdtype fl="d18" id="3" name="logic" left="31" right="0"/>
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</typetable>
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</netlist>
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</verilator_xml>
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