forked from github/verilator
Add parameter values in XML. #2110.
This commit is contained in:
Wilson Snyder
parent
47803c3591
commit
81e8127168
2
Changes
2
Changes
@ -11,6 +11,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
|
||||
|
||||
*** Support $readmem/$writemem with assoc arrarys. Closes #2100. [agrobman]
|
||||
|
||||
**** Add parameter values in XML. #2110. [Pieter Kapsenberg]
|
||||
|
||||
**** Add error on misused define. [Topa Tota]
|
||||
|
||||
|
||||
|
||||
@ -299,7 +299,7 @@ private:
|
||||
return (!nodep->isSigPublic() // Can't elim publics!
|
||||
&& !nodep->isIO()
|
||||
&& ((nodep->isTemp() && !nodep->isTrace())
|
||||
|| (nodep->isParam() && !nodep->isTrace())
|
||||
|| (nodep->isParam() && !nodep->isTrace() && !v3Global.opt.xmlOnly())
|
||||
|| m_elimUserVars)); // Post-Trace can kill most anything
|
||||
}
|
||||
|
||||
|
||||
@ -140,6 +140,8 @@ class EmitXmlFileVisitor : public AstNVisitor {
|
||||
if (nodep->isSigPublic()) puts(" public=\"true\"");
|
||||
if (nodep->isSigUserRdPublic()) puts(" public_flat_rd=\"true\"");
|
||||
if (nodep->isSigUserRWPublic()) puts(" public_flat_rw=\"true\"");
|
||||
if (nodep->isGParam()) puts(" param=\"true\"");
|
||||
else if (nodep->isParam()) puts(" localparam=\"true\"");
|
||||
if (nodep->attrScBv()) puts(" sc_bv=\"true\"");
|
||||
if (nodep->attrScClocked()) puts(" sc_clock=\"true\"");
|
||||
if (nodep->attrSFormat()) puts(" sformat=\"true\"");
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
</module_files>
|
||||
<cells>
|
||||
<cell fl="d6" name="t" submodname="t" hier="t">
|
||||
<cell fl="d18" name="cell1" submodname="mod1" hier="t.cell1"/>
|
||||
<cell fl="d19" name="cell1" submodname="mod1__W4" hier="t.cell1"/>
|
||||
<cell fl="d24" name="cell2" submodname="mod2" hier="t.cell2"/>
|
||||
</cell>
|
||||
</cells>
|
||||
@ -22,57 +22,64 @@
|
||||
<var fl="d13" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
|
||||
<var fl="d14" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
|
||||
<var fl="d16" name="between" dtype_id="2" vartype="logic" origName="between"/>
|
||||
<instance fl="d18" name="cell1" defName="mod1" origName="cell1">
|
||||
<port fl="d18" name="q" direction="out" portIndex="1">
|
||||
<varref fl="d18" name="between" dtype_id="2"/>
|
||||
<instance fl="d19" name="cell1" defName="mod1__W4" origName="cell1">
|
||||
<port fl="d19" name="q" direction="out" portIndex="1">
|
||||
<varref fl="d19" name="between" dtype_id="2"/>
|
||||
</port>
|
||||
<port fl="d21" name="clk" direction="in" portIndex="2">
|
||||
<varref fl="d21" name="clk" dtype_id="1"/>
|
||||
<port fl="d20" name="clk" direction="in" portIndex="2">
|
||||
<varref fl="d20" name="clk" dtype_id="1"/>
|
||||
</port>
|
||||
<port fl="d22" name="d" direction="in" portIndex="3">
|
||||
<varref fl="d22" name="d" dtype_id="2"/>
|
||||
<port fl="d21" name="d" direction="in" portIndex="3">
|
||||
<varref fl="d21" name="d" dtype_id="2"/>
|
||||
</port>
|
||||
</instance>
|
||||
<instance fl="d24" name="cell2" defName="mod2" origName="cell2">
|
||||
<port fl="d24" name="d" direction="in" portIndex="1">
|
||||
<varref fl="d24" name="between" dtype_id="2"/>
|
||||
</port>
|
||||
<port fl="d27" name="q" direction="out" portIndex="2">
|
||||
<varref fl="d27" name="q" dtype_id="2"/>
|
||||
<port fl="d25" name="q" direction="out" portIndex="2">
|
||||
<varref fl="d25" name="q" dtype_id="2"/>
|
||||
</port>
|
||||
<port fl="d29" name="clk" direction="in" portIndex="3">
|
||||
<varref fl="d29" name="clk" dtype_id="1"/>
|
||||
<port fl="d26" name="clk" direction="in" portIndex="3">
|
||||
<varref fl="d26" name="clk" dtype_id="1"/>
|
||||
</port>
|
||||
</instance>
|
||||
</module>
|
||||
<module fl="d33" name="mod1" origName="mod1">
|
||||
<var fl="d35" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
|
||||
<var fl="d36" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
|
||||
<var fl="d37" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
|
||||
<always fl="d39">
|
||||
<sentree fl="d39">
|
||||
<senitem fl="d39" edgeType="POS">
|
||||
<varref fl="d39" name="clk" dtype_id="1"/>
|
||||
<module fl="d30" name="mod1__W4" origName="mod1">
|
||||
<var fl="d31" name="WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">
|
||||
<const fl="d18" name="32'sh4" dtype_id="3"/>
|
||||
</var>
|
||||
<var fl="d33" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
|
||||
<var fl="d34" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
|
||||
<var fl="d35" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
|
||||
<var fl="d38" name="IGNORED" dtype_id="3" vartype="logic" origName="IGNORED" localparam="true">
|
||||
<const fl="d38" name="32'sh1" dtype_id="3"/>
|
||||
</var>
|
||||
<always fl="d40">
|
||||
<sentree fl="d40">
|
||||
<senitem fl="d40" edgeType="POS">
|
||||
<varref fl="d40" name="clk" dtype_id="1"/>
|
||||
</senitem>
|
||||
</sentree>
|
||||
<assigndly fl="d40" dtype_id="2">
|
||||
<varref fl="d40" name="d" dtype_id="2"/>
|
||||
<varref fl="d40" name="q" dtype_id="2"/>
|
||||
<assigndly fl="d41" dtype_id="2">
|
||||
<varref fl="d41" name="d" dtype_id="2"/>
|
||||
<varref fl="d41" name="q" dtype_id="2"/>
|
||||
</assigndly>
|
||||
</always>
|
||||
</module>
|
||||
<module fl="d44" name="mod2" origName="mod2">
|
||||
<var fl="d46" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
|
||||
<var fl="d47" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
|
||||
<var fl="d48" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
|
||||
<contassign fl="d51" dtype_id="2">
|
||||
<varref fl="d51" name="d" dtype_id="2"/>
|
||||
<varref fl="d51" name="q" dtype_id="2"/>
|
||||
<module fl="d45" name="mod2" origName="mod2">
|
||||
<var fl="d47" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
|
||||
<var fl="d48" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
|
||||
<var fl="d49" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
|
||||
<contassign fl="d52" dtype_id="2">
|
||||
<varref fl="d52" name="d" dtype_id="2"/>
|
||||
<varref fl="d52" name="q" dtype_id="2"/>
|
||||
</contassign>
|
||||
</module>
|
||||
<typetable fl="a0">
|
||||
<basicdtype fl="d46" id="1" name="logic"/>
|
||||
<basicdtype fl="d47" id="1" name="logic"/>
|
||||
<basicdtype fl="d13" id="2" name="logic" left="3" right="0"/>
|
||||
<basicdtype fl="d18" id="3" name="logic" left="31" right="0"/>
|
||||
</typetable>
|
||||
</netlist>
|
||||
</verilator_xml>
|
||||
|
||||
@ -13,29 +13,30 @@ module t (/*AUTOARG*/
|
||||
input [3:0] d;
|
||||
output wire [3:0] q;
|
||||
|
||||
logic [3:0] between;
|
||||
logic [3:0] between;
|
||||
|
||||
mod1 cell1 (.q(between),
|
||||
/*AUTOINST*/
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.d (d[3:0]));
|
||||
mod1 #(.WIDTH(4))
|
||||
cell1 (.q(between),
|
||||
.clk (clk),
|
||||
.d (d[3:0]));
|
||||
|
||||
mod2 cell2 (.d(between),
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.q (q[3:0]),
|
||||
// Inputs
|
||||
.clk (clk));
|
||||
mod2
|
||||
cell2 (.d(between),
|
||||
.q (q[3:0]),
|
||||
.clk (clk));
|
||||
|
||||
endmodule
|
||||
|
||||
module mod1
|
||||
(
|
||||
input clk,
|
||||
input [3:0] d,
|
||||
output logic [3:0] q
|
||||
#(parameter WIDTH = 32)
|
||||
(
|
||||
input clk,
|
||||
input [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q
|
||||
);
|
||||
|
||||
localparam IGNORED = 1;
|
||||
|
||||
always @(posedge clk)
|
||||
q <= d;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user