forked from github/verilator
27 lines
632 B
Systemverilog
27 lines
632 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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// bug601
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module t (
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input clk,
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input [3:0] in3, // worky
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input [0:0] in2 [3:0], // worky
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input in1 [3:0], // no worky
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input [1:0] sel,
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output reg out1,
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output reg out2,
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output reg out3
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);
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always @(posedge clk) begin
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out3 <= in3[sel] ? in3[sel] : out3;
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out2 <= in2[sel] ? in2[sel] : out2;
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out1 <= in1[sel] ? in1[sel] : out1; // breaks
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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