Fix array extraction of implicit vars, bug601.

Changes

@@ -19,6 +19,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix package import preventing local var, bug599.  [Jeremy Bennett]
 
+****  Fix array extraction of implicit vars, bug601.  [Joe Eiler]
+
 
 * Verilator 3.843 2012/12/01
 

src/V3Width.cpp

@@ -676,6 +676,10 @@ private:
 	    // calculation would return identical values.  Therefore we can directly replace the width
 	    nodep->widthForce(nodep->rangep()->elementsConst(), nodep->rangep()->elementsConst());
 	}
+	else if (nodep->implicit()) {
+	    // Parameters may notice implicitness and change to different dtype
+	    nodep->widthForce(1,1);
+	}
 	// else width in node is correct; it was set based on keyword().width()
 	// at construction time.  Ditto signed, so "unsigned byte" etc works right.
 	nodep->cvtRangeConst();

test_regress/t/t_var_vec_sel.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    v_flags2 => ["--lint-only"],
+    fails=>0,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    );
+
+ok(1);
+1;

test_regress/t/t_var_vec_sel.v

@@ -0,0 +1,26 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+// bug601
+
+module t (
+   input       clk,
+   input [3:0] in3, // worky
+   input [0:0] in2 [3:0], // worky
+   input       in1 [3:0], // no worky
+   input [1:0] sel,
+   output reg  out1,
+   output reg  out2,
+   output reg  out3
+   );
+
+   always @(posedge clk) begin
+      out3 <= in3[sel] ? in3[sel] : out3;
+      out2 <= in2[sel] ? in2[sel] : out2;
+      out1 <= in1[sel] ? in1[sel] : out1; // breaks
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule