verilator/test_regress/t/t_var_escape.out
2016-05-07 14:10:33 -04:00

164 lines
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$version Generated by VerilatedVcd $end
$date Tue Jul 24 18:44:43 2012
$end
$timescale 1ns $end
$scope module top $end
$var wire 1 * 9num $end
$var wire 1 + bra[ket]slash/dash-colon:9backslash\done $end
$var wire 1 ' clk $end
$var wire 1 ) double__underscore $end
$var wire 1 ( escaped_normal $end
$scope module t $end
$var wire 1 * 9num $end
$var wire 32 & a0.cyc [31:0] $end
$var wire 1 + bra[ket]slash/dash-colon:9backslash\done $end
$var wire 1 $ check:alias $end
$var wire 1 % check;alias $end
$var wire 1 $ check_alias $end
$var wire 1 ' clk $end
$var wire 32 # cyc [31:0] $end
$var wire 1 ) double__underscore $end
$var wire 1 ( escaped_normal $end
$var wire 32 & other.cyc [31:0] $end
$var wire 1 $ wire $end
$scope module a0 $end
$var wire 32 # cyc [31:0] $end
$upscope $end
$scope module mod.with_dot $end
$var wire 32 # cyc [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
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