forked from github/verilator
Change --l2-name default to remove 'v' naming.
This commit is contained in:
Wilson Snyder
parent
691de22ae3
commit
6b32bb635d
5
Changes
5
Changes
@ -10,7 +10,10 @@ indicates the contributor was also the author of the fix; Thanks!
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** Support command-line -G/+pvalue param overrides, bug1045. [Stefan Wallentowitz]
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*** Add --l2-name option for controlling "v" naming, bug1050.
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*** The default l2 scope name is now the same as the top-level module, bug1050.
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Use "--l2-name v" for the historical behavior.
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*** Add --l2-name option for controlling "v" naming.
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* Verilator 3.882 2016-03-01
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@ -789,11 +789,12 @@ in the Make variable LDLIBS, not LDFLAGS.)
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=item --l2-name I<value>
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Instead of using the module name when showing Verilog scope, use the name
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provided. Default is "--l2-name v" and is used to standardize some wrapping
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methodologies.
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provided. This allows simplifying some Verilator-embedded modeling
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methodologies. Default is an l2-name matching the top module. The default
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before 3.884 was "--l2-name v"
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The program "module t; initial $display("= %m"); endmodule" will show by
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default "= t". With "--l2-name v" it will print "= v".
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For example, the program "module t; initial $display("%m"); endmodule" will
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show by default "t". With "--l2-name v" it will print "v".
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=item --language I<value>
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@ -1250,7 +1250,7 @@ V3Options::V3Options() {
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m_makeDir = "obj_dir";
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m_bin = "";
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m_flags = "";
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m_l2Name = "v";
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m_l2Name = "";
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m_unusedRegexp = "*unused*";
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m_xAssign = "fast";
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@ -19,7 +19,7 @@ execute (
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check_finished=>0,
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fails=> $Self->{vlt},
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expect=>
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'%Error: t_assert_synth.v:\d+: Assertion failed in top.v: synthesis full_case'
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'%Error: t_assert_synth.v:\d+: Assertion failed in top.t: synthesis full_case'
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);
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ok(1);
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@ -19,7 +19,7 @@ execute (
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check_finished=>0,
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fails => $Self->{v3},
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expect=>
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'%Error: t_assert_synth.v:\d+: Assertion failed in top.v: synthesis parallel_case'
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'%Error: t_assert_synth.v:\d+: Assertion failed in top.t: synthesis parallel_case'
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);
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ok(1);
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@ -12,11 +12,11 @@ compile (
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verilator_make_gcc => 0,
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fails => 1,
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expect=>
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'%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: v.rst2_bad_n
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'%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: t.rst2_bad_n
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%Warning-CDCRSTLOGIC: Use "/\* verilator lint_off CDCRSTLOGIC \*/" and lint_on around source to disable this message.
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%Warning-CDCRSTLOGIC: See details in obj_dir/t_cdc_async_bad/Vt_cdc_async_bad__cdc.txt
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%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: v.rst6a_bad_n
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%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: v.rst6b_bad_n
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%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: t.rst6a_bad_n
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%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: t.rst6b_bad_n
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%Error: Exiting due to.*',
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);
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@ -77,7 +77,7 @@
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input toggle;
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always @ (posedge clk) begin
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%000002 if (toggle) begin
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// CHECK_COVER(-1,"top.v.a*",2)
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// CHECK_COVER(-1,"top.t.a*",2)
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// t.a1 and t.a2 collapse to a count of 2
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end
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if (toggle) begin
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@ -100,11 +100,11 @@
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always @ (posedge clk) begin
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%000000 if (0) begin
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// CHECK_COVER(-1,"top.v.b*",0)
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// CHECK_COVER(-1,"top.t.b*",0)
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// Make sure that we don't optimize away zero buckets
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end
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%000002 if (toggle) begin
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// CHECK_COVER(-1,"top.v.b*",2)
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// CHECK_COVER(-1,"top.t.b*",2)
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// t.b1 and t.b2 collapse to a count of 2
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end
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if (toggle) begin
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@ -133,10 +133,10 @@
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input external;
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begin
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%000001 if (toggle) begin
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// CHECK_COVER(-1,"top.v.t1",1)
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// CHECK_COVER(-1,"top.t.t1",1)
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end
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%000001 if (external) begin
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// CHECK_COVER(-1,"top.v.t1",1)
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// CHECK_COVER(-1,"top.t.t1",1)
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$write("[%0t] Got external pulse\n", $time);
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end
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end
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@ -161,7 +161,7 @@
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// verilator coverage_on
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always @ (posedge clk) begin
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%000001 if (toggle) begin
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// CHECK_COVER(-1,"top.v.o1",1)
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// CHECK_COVER(-1,"top.t.o1",1)
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// because under coverage_module_off
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end
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end
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@ -76,7 +76,7 @@ module alpha (/*AUTOARG*/
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input toggle;
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always @ (posedge clk) begin
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if (toggle) begin
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// CHECK_COVER(-1,"top.v.a*",2)
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// CHECK_COVER(-1,"top.t.a*",2)
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// t.a1 and t.a2 collapse to a count of 2
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end
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if (toggle) begin
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@ -99,11 +99,11 @@ module beta (/*AUTOARG*/
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always @ (posedge clk) begin
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if (0) begin
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// CHECK_COVER(-1,"top.v.b*",0)
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// CHECK_COVER(-1,"top.t.b*",0)
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// Make sure that we don't optimize away zero buckets
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end
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if (toggle) begin
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// CHECK_COVER(-1,"top.v.b*",2)
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// CHECK_COVER(-1,"top.t.b*",2)
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// t.b1 and t.b2 collapse to a count of 2
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end
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if (toggle) begin
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@ -132,10 +132,10 @@ module tsk (/*AUTOARG*/
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input external;
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begin
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if (toggle) begin
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// CHECK_COVER(-1,"top.v.t1",1)
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// CHECK_COVER(-1,"top.t.t1",1)
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end
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if (external) begin
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// CHECK_COVER(-1,"top.v.t1",1)
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// CHECK_COVER(-1,"top.t.t1",1)
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$write("[%0t] Got external pulse\n", $time);
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end
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end
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@ -160,7 +160,7 @@ module off (/*AUTOARG*/
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// verilator coverage_on
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always @ (posedge clk) begin
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if (toggle) begin
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// CHECK_COVER(-1,"top.v.o1",1)
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// CHECK_COVER(-1,"top.t.o1",1)
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// because under coverage_module_off
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end
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end
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@ -20,7 +20,7 @@ execute (
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# Allow old Perl format dump, or new binary dump
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# Check that the hierarchy doesn't include __PVT__
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# Otherwise our coverage reports would look really ugly
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file_grep ($Self->{coverage_filename}, qr/(top\.v\.sub.*.cyc_eq_5)/)
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file_grep ($Self->{coverage_filename}, qr/(top\.t\.sub.*.cyc_eq_5)/)
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if $Self->{vlt};
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ok(1);
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@ -95,25 +95,25 @@ module alpha (/*AUTOARG*/
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input clk;
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input toggle;
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// CHECK_COVER(-1,"top.v.a*",4)
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// CHECK_COVER(-1,"top.t.a*",4)
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// 2 edges * (t.a1 and t.a2)
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input [7:0] cyc_copy;
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// CHECK_COVER(-1,"top.v.a*","cyc_copy[0]",22)
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// CHECK_COVER(-2,"top.v.a*","cyc_copy[1]",10)
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// CHECK_COVER(-3,"top.v.a*","cyc_copy[2]",4)
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// CHECK_COVER(-4,"top.v.a*","cyc_copy[3]",2)
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// CHECK_COVER(-5,"top.v.a*","cyc_copy[4]",0)
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// CHECK_COVER(-6,"top.v.a*","cyc_copy[5]",0)
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// CHECK_COVER(-7,"top.v.a*","cyc_copy[6]",0)
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// CHECK_COVER(-8,"top.v.a*","cyc_copy[7]",0)
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// CHECK_COVER(-1,"top.t.a*","cyc_copy[0]",22)
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// CHECK_COVER(-2,"top.t.a*","cyc_copy[1]",10)
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// CHECK_COVER(-3,"top.t.a*","cyc_copy[2]",4)
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// CHECK_COVER(-4,"top.t.a*","cyc_copy[3]",2)
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// CHECK_COVER(-5,"top.t.a*","cyc_copy[4]",0)
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// CHECK_COVER(-6,"top.t.a*","cyc_copy[5]",0)
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// CHECK_COVER(-7,"top.t.a*","cyc_copy[6]",0)
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// CHECK_COVER(-8,"top.t.a*","cyc_copy[7]",0)
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reg toggle_internal;
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// CHECK_COVER(-1,"top.v.a*",4)
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// CHECK_COVER(-1,"top.t.a*",4)
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// 2 edges * (t.a1 and t.a2)
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output reg toggle_up;
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// CHECK_COVER(-1,"top.v.a*",4)
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// CHECK_COVER(-1,"top.t.a*",4)
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// 2 edges * (t.a1 and t.a2)
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always @ (posedge clk) begin
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@ -130,7 +130,7 @@ module beta (/*AUTOARG*/
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input clk;
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input toggle_up;
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// CHECK_COVER(-1,"top.v.b1","toggle_up",2)
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// CHECK_COVER(-1,"top.t.b1","toggle_up",2)
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/* verilator public_module */
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@ -150,6 +150,6 @@ module off (/*AUTOARG*/
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// verilator coverage_on
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input toggle;
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// CHECK_COVER(-1,"top.v.o1","toggle",2)
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// CHECK_COVER(-1,"top.t.o1","toggle",2)
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endmodule
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@ -13,11 +13,11 @@ compile (
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execute (
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check_finished=>1,
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expect=>dequote(
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q{[0] In top.v: Hi
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[0] In top.v.sub (sub)
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[0] In top.v.sub.subblock (sub)
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[0] In top.v.sub2 (sub2)
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[0] In top.v.sub2.subblock2 (sub2)
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q{[0] In top.t: Hi
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[0] In top.t.sub (sub)
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[0] In top.t.sub.subblock (sub)
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[0] In top.t.sub2 (sub2)
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[0] In top.t.sub2.subblock2 (sub2)
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[0] Back \ Quote "
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[0] %b=000001100 %0b=1100 %b=00000101010111011101110111100110011001100 %0b=101010111011101110111100110011001100 %b=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0b=1010101111000001001000110100010101100111100000010010001101000101011001111000
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[0] %B=000001100 %0B=1100 %B=00000101010111011101110111100110011001100 %0B=101010111011101110111100110011001100 %B=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0B=1010101111000001001000110100010101100111100000010010001101000101011001111000
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@ -16,11 +16,11 @@ compile (
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execute (
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check_finished=>1,
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expect=>dequote(
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q{[0] In top.v: Hi
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[0] In top.v.sub (sub)
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[0] In top.v.sub.subblock (sub)
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[0] In top.v.sub2 (sub2)
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[0] In top.v.sub2.subblock2 (sub2)
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q{[0] In top.t: Hi
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[0] In top.t.sub (sub)
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[0] In top.t.sub.subblock (sub)
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[0] In top.t.sub2 (sub2)
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[0] In top.t.sub2.subblock2 (sub2)
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[0] Back \ Quote "
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[0] %b=000001100 %0b=1100 %b=00000101010111011101110111100110011001100 %0b=101010111011101110111100110011001100 %b=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0b=1010101111000001001000110100010101100111100000010010001101000101011001111000
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[0] %B=000001100 %0B=1100 %B=00000101010111011101110111100110011001100 %0B=101010111011101110111100110011001100 %B=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0B=1010101111000001001000110100010101100111100000010010001101000101011001111000
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@ -90,7 +90,7 @@ checkResult (bool p,
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int main ()
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{
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Vt_dpi_accessors *dut = new Vt_dpi_accessors ("dut");
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svSetScope (svGetScopeFromName ("dut.v"));
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svSetScope (svGetScopeFromName ("dut.t"));
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// evaluate the model with no signal changes to get the initial blocks
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// executed.
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@ -22,8 +22,8 @@ dpii_display_call: constant
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dpii_display_call: constant_value
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one10=0000000a
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dpii_display_call: one10=0000000a
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Mod=top.v 16= 10 10=0000000a
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dpii_display_call: Mod=top.v 16= 10 10=0000000a
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Mod=top.t 16= 10 10=0000000a
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dpii_display_call: Mod=top.t 16= 10 10=0000000a
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*-* All Finished *-*
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}),
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);
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@ -11,7 +11,7 @@ compile (
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v_flags2 => ["--lint-only"],
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fails=>$Self->{v3},
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expect=>
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'%Error: t/t_dpi_dup_bad.v:\d+: Duplicate declaration of DPI function with different formal arguments: v.oth_f_int2
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'%Error: t/t_dpi_dup_bad.v:\d+: Duplicate declaration of DPI function with different formal arguments: t.oth_f_int2
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%Error: t/t_dpi_dup_bad.v:\d+: ... New prototype: pure int dpii_fa_bit \(int, int\)
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%Error: t/t_dpi_dup_bad.v:\d+: ... Original prototype: int dpii_fa_bit \(int\)
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%Error: Exiting due to .*'
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@ -13,17 +13,17 @@ compile (
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execute (
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check_finished=>1,
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expect=>quotemeta(
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q{created tag with scope = top.v.b.gen[0].tag
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created tag with scope = top.v.b.gen[1].tag
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created tag with scope = top.v.tag
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mod a has scope = top.v
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mod a has tag = top.v.tag
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mod b has scope = top.v.b
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mod b has tag = top.v.tag
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mod c has scope = top.v.b.gen[0].c
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mod c has tag = top.v.b.gen[0].tag
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mod c has scope = top.v.b.gen[1].c
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mod c has tag = top.v.b.gen[1].tag
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q{created tag with scope = top.t.b.gen[0].tag
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created tag with scope = top.t.b.gen[1].tag
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created tag with scope = top.t.tag
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mod a has scope = top.t
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mod a has tag = top.t.tag
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mod b has scope = top.t.b
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mod b has tag = top.t.tag
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mod c has scope = top.t.b.gen[0].c
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mod c has tag = top.t.b.gen[0].tag
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mod c has scope = top.t.b.gen[1].c
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mod c has tag = top.t.b.gen[1].tag
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*-* All Finished *-*}),
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);
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@ -16,7 +16,7 @@ compile (
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execute (
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check_finished=>1,
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expect=>
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'\] (%m|.*v\.ps): Clocked
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'\] (%m|.*t\.ps): Clocked
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',
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);
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@ -20,7 +20,7 @@ if ($Self->{vlt}) {
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execute (
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check_finished=>1,
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expect=>
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'\] (%m|.*v\.ps): Clocked
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'\] (%m|.*t\.ps): Clocked
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',
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);
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@ -16,7 +16,7 @@ compile (
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execute (
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check_finished=>1,
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expect=>
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'\] (%m|.*v\.ps): Clocked
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'\] (%m|.*t\.ps): Clocked
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',
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);
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@ -16,7 +16,7 @@ compile (
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execute (
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check_finished=>1,
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expect=>
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'\] (%m|.*v\.ps): Clocked
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'\] (%m|.*t\.ps): Clocked
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',
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);
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@ -16,7 +16,7 @@ compile (
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make_top_shell => 0,
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make_main => 0,
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expect=>
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'%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:\d+: Signal has multiple driving blocks: v.mem
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'%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:\d+: Signal has multiple driving blocks: t.mem
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%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:\d+: ... Location of first driving block
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%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:\d+: ... Location of other driving block
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%Warning-MULTIDRIVEN: Use ".*" and lint_on around source to disable this message.
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@ -16,7 +16,7 @@ compile (
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expect=>
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'%Error: Circular logic when ordering code .*
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%Error: Example path: t/t_order_loop_bad.v:\d+: ALWAYS
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%Error: Example path: t/t_order_loop_bad.v:\d+: v.ready
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%Error: Example path: t/t_order_loop_bad.v:\d+: t.ready
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%Error: Example path: t/t_order_loop_bad.v:\d+: ACTIVE
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.*',
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);
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@ -49,11 +49,7 @@ module t;
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$swrite(str2, "mod=%m");
|
||||
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
|
||||
`ifdef verilator
|
||||
if (str2 !== "mod=top.v") $stop;
|
||||
`else
|
||||
if (str2 !== "mod=top.t") $stop;
|
||||
`endif
|
||||
|
||||
$swrite(str2, "lib=%l");
|
||||
`ifdef TEST_VERBOSE $display("chkl %0s",str2); `endif
|
||||
|
||||
@ -5,7 +5,7 @@ $timescale 1ns $end
|
||||
|
||||
$scope module top $end
|
||||
$var wire 1 $ clk $end
|
||||
$scope module v $end
|
||||
$scope module t $end
|
||||
$var wire 1 $ clk $end
|
||||
$var wire 32 # cyc [31:0] $end
|
||||
$upscope $end
|
||||
|
||||
@ -5,7 +5,7 @@ $timescale 1ns $end
|
||||
|
||||
$scope module top $end
|
||||
$var wire 1 $ clk $end
|
||||
$scope module v $end
|
||||
$scope module t $end
|
||||
$var wire 1 $ clk $end
|
||||
$var wire 32 # cyc [31:0] $end
|
||||
$upscope $end
|
||||
|
||||
@ -5,7 +5,7 @@ $timescale 1ns $end
|
||||
|
||||
$scope module top $end
|
||||
$var wire 1 $ clk $end
|
||||
$scope module v $end
|
||||
$scope module t $end
|
||||
$var wire 1 $ clk $end
|
||||
$var wire 32 # cyc [31:0] $end
|
||||
$upscope $end
|
||||
|
||||
@ -5,7 +5,7 @@ $timescale 1ns $end
|
||||
|
||||
$scope module top $end
|
||||
$var wire 1 $ clk $end
|
||||
$scope module v $end
|
||||
$scope module t $end
|
||||
$var wire 1 $ clk $end
|
||||
$var wire 32 # cyc [31:0] $end
|
||||
$upscope $end
|
||||
|
||||
@ -5,7 +5,7 @@ $timescale 1ns $end
|
||||
|
||||
$scope module top $end
|
||||
$var wire 1 $ clk $end
|
||||
$scope module v $end
|
||||
$scope module t $end
|
||||
$var wire 1 $ clk $end
|
||||
$var wire 32 # cyc [31:0] $end
|
||||
$upscope $end
|
||||
|
||||
@ -5,7 +5,7 @@ $timescale 1ns $end
|
||||
|
||||
$scope module top $end
|
||||
$var wire 1 $ clk $end
|
||||
$scope module v $end
|
||||
$scope module t $end
|
||||
$var wire 1 $ clk $end
|
||||
$var wire 32 # cyc [31:0] $end
|
||||
$upscope $end
|
||||
|
||||
@ -5,7 +5,7 @@ $timescale 1ns $end
|
||||
|
||||
$scope module top $end
|
||||
$var wire 1 $ clk $end
|
||||
$scope module v $end
|
||||
$scope module t $end
|
||||
$var wire 1 $ clk $end
|
||||
$var wire 32 # cyc [31:0] $end
|
||||
$upscope $end
|
||||
|
||||
@ -8,7 +8,7 @@ $timescale 1ns $end
|
||||
$scope module $unit $end
|
||||
$var wire 1 # global_bit $end
|
||||
$upscope $end
|
||||
$scope module v $end
|
||||
$scope module t $end
|
||||
$var wire 1 9 clk $end
|
||||
$var wire 32 $ cyc [31:0] $end
|
||||
$var real 64 3 v_arr_real(0) $end
|
||||
|
||||
@ -8,7 +8,7 @@ $timescale 1ns $end
|
||||
$scope module $unit $end
|
||||
$var wire 1 # global_bit $end
|
||||
$upscope $end
|
||||
$scope module v $end
|
||||
$scope module t $end
|
||||
$var wire 1 9 clk $end
|
||||
$var wire 32 $ cyc [31:0] $end
|
||||
$var real 64 3 v_arr_real(0) $end
|
||||
|
||||
@ -8,7 +8,7 @@ $timescale 1ns $end
|
||||
$scope module $unit $end
|
||||
$var wire 1 # global_bit $end
|
||||
$upscope $end
|
||||
$scope module v $end
|
||||
$scope module t $end
|
||||
$var wire 1 D clk $end
|
||||
$var wire 32 $ cyc [31:0] $end
|
||||
$var real 64 > v_arr_real(0) $end
|
||||
|
||||
@ -6,7 +6,7 @@ $timescale 1ns $end
|
||||
$scope module top $end
|
||||
$var wire 1 6 CLK $end
|
||||
$var wire 1 7 RESET $end
|
||||
$scope module v $end
|
||||
$scope module t $end
|
||||
$var wire 1 6 CLK $end
|
||||
$var wire 1 # RESET $end
|
||||
$var wire 32 $ val [31:0] $end
|
||||
|
||||
@ -33,7 +33,7 @@ int main(int argc, char **argv, char **env) {
|
||||
top->CLK = (main_time/dt_2)%2;
|
||||
top->eval();
|
||||
|
||||
top->v->glbl->setGSR(main_time < 7);
|
||||
top->t->glbl->setGSR(main_time < 7);
|
||||
|
||||
tfp->dump((unsigned int)(main_time));
|
||||
++main_time;
|
||||
|
||||
@ -33,7 +33,7 @@ int main(int argc, char **argv, char **env) {
|
||||
top->CLK = (main_time/dt_2)%2;
|
||||
top->eval();
|
||||
|
||||
top->v->glbl->GSR = (main_time < 7);
|
||||
top->t->glbl->GSR = (main_time < 7);
|
||||
|
||||
tfp->dump((unsigned int)(main_time));
|
||||
++main_time;
|
||||
|
||||
@ -19,7 +19,7 @@ compile (
|
||||
execute (
|
||||
fails => $Self->{vlt},
|
||||
expect=>
|
||||
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated
|
||||
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
|
||||
%Error: t/t_uniqueif.v:\d+: Verilog \$stop
|
||||
.*',
|
||||
);
|
||||
|
||||
@ -19,7 +19,7 @@ compile (
|
||||
execute (
|
||||
fails => $Self->{vlt},
|
||||
expect=>
|
||||
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated
|
||||
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
|
||||
%Error: t/t_uniqueif.v:\d+: Verilog \$stop
|
||||
.*',
|
||||
);
|
||||
|
||||
@ -19,7 +19,7 @@ compile (
|
||||
execute (
|
||||
fails => $Self->{vlt},
|
||||
expect=>
|
||||
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated
|
||||
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
|
||||
%Error: t/t_uniqueif.v:\d+: Verilog \$stop
|
||||
.*',
|
||||
);
|
||||
|
||||
@ -19,7 +19,7 @@ compile (
|
||||
execute (
|
||||
fails => $Self->{vlt},
|
||||
expect=>
|
||||
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated
|
||||
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
|
||||
%Error: t/t_uniqueif.v:\d+: Verilog \$stop
|
||||
.*',
|
||||
);
|
||||
|
||||
@ -12,13 +12,13 @@ top_filename("t/t_unopt_combo.v");
|
||||
compile (
|
||||
fails=>$Self->{vlt},
|
||||
expect=>
|
||||
'%Warning-UNOPTFLAT: t/t_unopt_combo.v:\d+: Signal unoptimizable: Feedback to clock or circular logic: v.c
|
||||
'%Warning-UNOPTFLAT: t/t_unopt_combo.v:\d+: Signal unoptimizable: Feedback to clock or circular logic: t.c
|
||||
%Warning-UNOPTFLAT: Use "/\* verilator lint_off UNOPTFLAT \*/" and lint_on around source to disable this message.
|
||||
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: v.c
|
||||
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: t.c
|
||||
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: ALWAYS
|
||||
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: v.b
|
||||
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: t.b
|
||||
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: ALWAYS
|
||||
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: v.c
|
||||
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: t.c
|
||||
%Error: Exiting due to '
|
||||
);
|
||||
|
||||
|
||||
@ -16,7 +16,7 @@ compile (
|
||||
fails => 1,
|
||||
expect=>
|
||||
'.*%Warning-UNOPTFLAT: Widest candidate vars to split:
|
||||
%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:\d+: v.x, width 3, fanout \d+
|
||||
%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:\d+: t.x, width 3, fanout \d+
|
||||
.*%Error: Exiting due to ',
|
||||
);
|
||||
|
||||
|
||||
@ -9,7 +9,7 @@ $timescale 1ns $end
|
||||
$var wire 1 ' clk $end
|
||||
$var wire 1 ) double__underscore $end
|
||||
$var wire 1 ( escaped_normal $end
|
||||
$scope module v $end
|
||||
$scope module t $end
|
||||
$var wire 1 * 9num $end
|
||||
$var wire 32 & a0.cyc [31:0] $end
|
||||
$var wire 1 + bra[ket]slash/dash-colon:9backslash\done $end
|
||||
|
||||
@ -6,7 +6,7 @@ $timescale 1ns $end
|
||||
$scope module top $end
|
||||
$var wire 1 # clk $end
|
||||
$var wire 1 $ reset_l $end
|
||||
$scope module v $end
|
||||
$scope module t $end
|
||||
$var wire 1 # clk $end
|
||||
$var wire 1 % inmod $end
|
||||
$var wire 32 & rawmod [31:0] $end
|
||||
|
||||
@ -13,14 +13,14 @@ compile (
|
||||
|
||||
execute (
|
||||
expect=>quotemeta(
|
||||
'ingen: {mod}.genblk1 top.v.genblk1
|
||||
d3a: {mod}.d3nameda top.v.d3nameda
|
||||
b2: {mod} top.v
|
||||
b3n: {mod}.b3named: top.v.b3named
|
||||
b3: {mod} top.v
|
||||
b4: {mod} top.v
|
||||
t1 {mod}.tsk top.v
|
||||
t2 {mod}.tsk top.v
|
||||
'ingen: {mod}.genblk1 top.t.genblk1
|
||||
d3a: {mod}.d3nameda top.t.d3nameda
|
||||
b2: {mod} top.t
|
||||
b3n: {mod}.b3named: top.t.b3named
|
||||
b3: {mod} top.t
|
||||
b4: {mod} top.t
|
||||
t1 {mod}.tsk top.t
|
||||
t2 {mod}.tsk top.t
|
||||
*-* All Finished *-*'),
|
||||
);
|
||||
|
||||
|
||||
@ -29,7 +29,7 @@ int main(int argc, char **argv, char **env) {
|
||||
#define CYCTIME 10
|
||||
|
||||
// Cycle the interpreter
|
||||
while (main_time < CYCTIME*top->v->CYCLES) {
|
||||
while (main_time < CYCTIME*top->vgen->CYCLES) {
|
||||
top->eval();
|
||||
main_time += CYCTIME/2;
|
||||
top->clk = !top->clk;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user