forked from github/verilator
15 lines
557 B
Plaintext
15 lines
557 B
Plaintext
%Error: t/t_var_dup2_bad.v:12: Duplicate declaration of signal: 'bad_o_w'
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: ... note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2)
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wire bad_o_w;
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^~~~~~~
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t/t_var_dup2_bad.v:9: ... Location of original declaration
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output bad_o_w,
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^~~~~~~
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%Error: t/t_var_dup2_bad.v:13: Duplicate declaration of signal: 'bad_o_r'
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reg bad_o_r;
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^~~~~~~
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t/t_var_dup2_bad.v:10: ... Location of original declaration
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output bad_o_r);
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^~~~~~~
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%Error: Exiting due to
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