forked from github/verilator
13 lines
797 B
Plaintext
13 lines
797 B
Plaintext
%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:14: Signal unoptimizable: Feedback to clock or circular logic: 't.x'
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wire [2:0] x;
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^
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... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
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t/t_unoptflat_simple_2.v:14: Example path: t.x
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t/t_unoptflat_simple_2.v:16: Example path: ASSIGNW
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t/t_unoptflat_simple_2.v:14: Example path: t.x
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%Warning-UNOPTFLAT: Widest candidate vars to split:
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%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:14: t.x, width 3, fanout 12
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%Warning-UNOPTFLAT: Most fanned out candidate vars to split:
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%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:14: t.x, width 3, fanout 12
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%Error: Exiting due to
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