forked from github/verilator
27 lines
459 B
Systemverilog
27 lines
459 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Wilson Snyder.
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// verilator lint_off UNUSED
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// verilator lint_off UNDRIVEN
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//bug858
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typedef struct packed {
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logic m_1;
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logic m_2;
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} struct_t;
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typedef struct packed {
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logic [94:0] m_1;
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logic m_2;
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} struct96_t;
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module t
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(
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input struct_t test_input,
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input struct96_t t96
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);
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endmodule
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