forked from github/verilator
223 lines
4.0 KiB
Plaintext
223 lines
4.0 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$date Wed Jan 8 07:26:16 2020
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$end
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$timescale 1ns $end
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$scope module top $end
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$var wire 1 /" clk $end
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$scope module $unit $end
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$var wire 1 # global_bit $end
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$upscope $end
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$scope module t $end
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$var wire 1 /" clk $end
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$var wire 32 + cyc [31:0] $end
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$var wire 8 h" unpacked_array(-1) [7:0] $end
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$var wire 8 g" unpacked_array(-2) [7:0] $end
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$var wire 8 i" unpacked_array(0) [7:0] $end
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$var real 64 E! v_arr_real(0) $end
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$var real 64 G! v_arr_real(1) $end
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$var wire 2 [ v_arrp [2:1] $end
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$var wire 4 c v_arrp_arrp [3:0] $end
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$var wire 4 k v_arrp_strp [3:0] $end
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$var wire 1 7" v_arru(1) $end
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$var wire 1 8" v_arru(2) $end
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$var wire 2 s v_arru_arrp(3) [2:1] $end
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$var wire 2 t v_arru_arrp(4) [2:1] $end
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$var wire 1 G" v_arru_arru(3)(1) $end
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$var wire 1 O" v_arru_arru(3)(2) $end
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$var wire 1 W" v_arru_arru(4)(1) $end
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$var wire 1 _" v_arru_arru(4)(2) $end
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$var wire 2 %! v_arru_strp(3) [1:0] $end
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$var wire 2 -! v_arru_strp(4) [1:0] $end
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$var wire 3 u! v_enumb [2:0] $end
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$var wire 32 e! v_enumed [31:0] $end
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$var wire 32 m! v_enumed2 [31:0] $end
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$var real 64 5! v_real $end
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$var wire 64 3 v_str32x2 [63:0] $end
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$var wire 2 C v_strp [1:0] $end
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$var wire 4 K v_strp_strp [3:0] $end
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$var wire 2 S v_unip_strp [1:0] $end
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$scope module p2 $end
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$var wire 32 !# PARAM [31:0] $end
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$upscope $end
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$scope module p3 $end
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$var wire 32 )# PARAM [31:0] $end
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$upscope $end
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$scope module unnamedblk1 $end
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$var wire 32 }! b [31:0] $end
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$scope module unnamedblk2 $end
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$var wire 32 '" a [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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1#
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b00000000000000000000000000000000 +
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b0000000000000000000000000000000000000000000000000000000011111111 3
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#55
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#60
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1/"
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