forked from github/verilator
766 lines
7.8 KiB
Plaintext
766 lines
7.8 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$date Sat Feb 23 20:18:07 2013
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$end
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$timescale 1ns $end
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$scope module top $end
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$var wire 1 $ clk $end
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$scope module t $end
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$var wire 1 $ clk $end
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$var wire 32 # cyc [31:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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1$
|
|
#291
|
|
0$
|
|
#292
|
|
b00000000000000000000000010010011 #
|
|
1$
|
|
#293
|
|
0$
|
|
#294
|
|
b00000000000000000000000010010100 #
|
|
1$
|
|
#295
|
|
0$
|
|
#296
|
|
b00000000000000000000000010010101 #
|
|
1$
|
|
#297
|
|
0$
|
|
#298
|
|
b00000000000000000000000010010110 #
|
|
1$
|
|
#299
|
|
0$
|