forked from github/verilator
39 lines
921 B
Systemverilog
39 lines
921 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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dataout,
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// Inputs
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clk, sel, d0, d1
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);
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input clk;
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input sel;
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logic [7:0] data [1:0][3:0];
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input [7:0] d0, d1;
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output wire [8*2*4-1:0] dataout;
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always_comb begin
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for ( integer j = 0; j <= 1; j++ ) begin
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if (sel)
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data[j] = '{ d0, d1, 8'h00, 8'h00 };
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else
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data[j] = '{ 8'h00, 8'h00, 8'h00, 8'h00 };
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end
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for ( integer j = 0; j <= 1; j++ ) begin
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data[j] = sel
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? '{ d0, d1, 8'h00, 8'h00 }
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: '{ 8'h00, 8'h00, 8'h00, 8'h00 };
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end
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end
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assign dataout = {data[0][0], data[0][1], data[0][2], data[0][3],
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data[1][0], data[1][1], data[1][2], data[1][3]};
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endmodule
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