forked from github/verilator
10 lines
465 B
Plaintext
10 lines
465 B
Plaintext
%Warning-LITENDIAN: t/t_select_bad_msb.v:11: Little bit endian vector: MSB < LSB of bit range: 0:22
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reg [0:22] backwd;
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^
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... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
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%Error: t/t_select_bad_msb.v:15: [1:4] Range extract has backward bit ordering, perhaps you wanted [4:1]
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: ... In instance t
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sel2 = mi[1:4];
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^
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%Error: Exiting due to
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