forked from github/verilator
15 lines
357 B
Systemverilog
15 lines
357 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Todd Strader.
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module secret_impl (
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input a,
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input oe,
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inout z,
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output y);
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assign z = oe ? a : 1'bz;
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assign y = z;
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endmodule
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