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Benchmark --protect-lib runtime, bug1519.

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This commit is contained in:
Todd Strader 2019-10-23 08:32:02 -04:00
parent 17ee8579a4
commit 3b33438e91
10 changed files with 101 additions and 48 deletions
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2
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@ -20,6 +20,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Fix bad-syntax crashes, bug1548, bug1550-1553, bug1557-1560, bug1563. [Eric Rippey]
**** Benchmark --protect-lib runtime, bug1519. [Todd Strader]
* Verilator 4.020 2019-10-06

3
test_regress/driver.pl
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@ -589,7 +589,8 @@ sub new {
xsim => 0,
xsim_flags => [split(/\s+/,("--nolog --sv --define XSIM --work $self->{name}=$self->{obj_dir}/xsim"))],
xsim_flags2 => [], # Overridden in some sim files
xsim_run_flags => [split(/\s+/,"--nolog --runall --lib $self->{name}=$self->{obj_dir}/xsim ")],
xsim_run_flags => [split(/\s+/,("--nolog --runall --lib $self->{name}=$self->{obj_dir}/xsim"
.($opt_trace ? " --debug all":"")))],
xsim_run_flags2 => [], # Overridden in some sim files
# Verilator
vlt => 0,

39
test_regress/t/t_noprot_lib.pl Executable file
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@ -0,0 +1,39 @@
#!/usr/bin/perl
# Makes the test run with tracing enabled by default, can be overridden
# with --notrace
unshift(@ARGV, "--trace");
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2019 by Todd Strader. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(
vlt => 1,
xsim => 1,
);
$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark};
top_filename("t/t_prot_lib.v");
# Tests the same code as t_prot_lib.pl but without --protect-lib
compile(
verilator_flags2 => ["t/t_prot_lib_secret.v"],
xsim_flags2 => ["t/t_prot_lib_secret.v"],
);
execute(
check_finished => 1,
);
if ($Self->{vlt} && $Self->{trace}) {
# We can see the ports of the secret module
file_grep("$Self->{obj_dir}/simx.vcd", qr/accum_in/);
# and we can see what's inside (because we didn't use --protect-lib)
file_grep("$Self->{obj_dir}/simx.vcd", qr/secret_/);
}
ok(1);
1;

13
test_regress/t/t_prot_lib.pl
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@ -1,4 +1,7 @@
#!/usr/bin/perl
# Makes the test run with tracing enabled by default, can be overridden
# with --notrace
unshift(@ARGV, "--trace");
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
@ -12,6 +15,8 @@ scenarios(
xsim => 1,
);
$Self->{sim_time} = $Self->{benchmark} * 100 if $Self->{benchmark};
# Always compile the secret file with Verilator no matter what simulator
# we are testing with
my $cmd = ["t/t_prot_lib_secret.pl", "--vlt"];
@ -26,21 +31,19 @@ while (1) {
compile(
verilator_flags2 => ["$secret_dir/secret.sv",
"--trace", "-LDFLAGS",
"-LDFLAGS",
"'-L../$secret_prefix -lsecret -static'"],
xsim_flags2 => ["$secret_dir/secret.sv"],
);
execute(
check_finished => 1,
xsim_run_flags2 => ["--debug",
"all",
"--sv_lib",
xsim_run_flags2 => ["--sv_lib",
"$secret_dir/libsecret",
"--dpi_absolute"],
);
if ($Self->{vlt}) {
if ($Self->{vlt} && $Self->{trace}) {
# We can see the ports of the secret module
file_grep("$Self->{obj_dir}/simx.vcd", qr/accum_in/);
# but we can't see what's inside

22
test_regress/t/t_prot_lib.v
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@ -15,11 +15,18 @@ if (cyc > 0 && sig``_in != sig``_out) begin \
end
module t (/*AUTOARG*/
// Inputs
clk
);
// Inputs
clk
);
input clk;
localparam last_cyc =
`ifdef TEST_BENCHMARK
`TEST_BENCHMARK;
`else
10;
`endif
genvar x;
generate
for (x = 0; x < 2; x = x + 1) begin: gen_loop
@ -27,12 +34,12 @@ module t (/*AUTOARG*/
reg [63:0] crc = 64'h5aef0c8d_d70a4497;
logic [31:0] accum_in;
logic [31:0] accum_out;
logic accum_bypass;
logic accum_bypass;
logic [31:0] accum_bypass_out;
logic [31:0] accum_out_expect;
logic [31:0] accum_bypass_out_expect;
logic s1_in;
logic s1_out;
logic s1_in;
logic s1_out;
logic [1:0] s2_in;
logic [1:0] s2_out;
logic [7:0] s8_in;
@ -108,7 +115,8 @@ module t (/*AUTOARG*/
if (cyc == 5) accum_bypass <= '1;
if (x == 0 && cyc == 10) begin
if (x == 0 && cyc == last_cyc) begin
$display("final cycle = %0d", cyc);
$write("*-* All Finished *-*\n");
$finish;
end

4
test_regress/t/t_prot_lib_inout_bad.out
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@ -1,5 +1,5 @@
%Error: Internal Error: t/t_prot_lib_inout_bad.v:8: ../V3ProtectLib.cpp:359: Unsupported port direction for protect-lib: INOUT
inout z,
^
inout z,
^
... See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Command Failed

8
test_regress/t/t_prot_lib_inout_bad.v
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@ -3,10 +3,10 @@
// without warranty, 2019 by Todd Strader.
module secret_impl (
input a,
input oe,
inout z,
output y);
input a,
input oe,
inout z,
output y);
assign z = oe ? a : 1'bz;
assign y = z;

48
test_regress/t/t_prot_lib_secret.v
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@ -2,31 +2,31 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
module secret_impl (
input [31:0] accum_in,
output wire [31:0] accum_out,
input accum_bypass,
output [31:0] accum_bypass_out,
input s1_in,
output logic s1_out,
input [1:0] s2_in,
output logic [1:0] s2_out,
input [7:0] s8_in,
output logic [7:0] s8_out,
input [32:0] s33_in,
output logic [32:0] s33_out,
input [63:0] s64_in,
output logic [63:0] s64_out,
input [64:0] s65_in,
output logic [64:0] s65_out,
input [128:0] s129_in,
output logic [128:0] s129_out,
input [3:0] [31:0] s4x32_in,
output logic [3:0] [31:0] s4x32_out,
input clk);
module secret (
input [31:0] accum_in,
output wire [31:0] accum_out,
input accum_bypass,
output [31:0] accum_bypass_out,
input s1_in,
output logic s1_out,
input [1:0] s2_in,
output logic [1:0] s2_out,
input [7:0] s8_in,
output logic [7:0] s8_out,
input [32:0] s33_in,
output logic [32:0] s33_out,
input [63:0] s64_in,
output logic [63:0] s64_out,
input [64:0] s65_in,
output logic [64:0] s65_out,
input [128:0] s129_in,
output logic [128:0] s129_out,
input [3:0] [31:0] s4x32_in,
output logic [3:0] [31:0] s4x32_out,
input clk);
logic [31:0] secret_accum_q = 0;
logic [31:0] secret_value = 7;
logic [31:0] secret_accum_q = 0;
logic [31:0] secret_value = 7;
initial $display("created %m");

4
test_regress/t/t_prot_lib_unpacked_bad.out
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@ -1,5 +1,5 @@
%Error: Internal Error: t/t_prot_lib_unpacked_bad.v:6: ../V3ProtectLib.cpp:347: Unsupported: unpacked arrays with protect-lib
input unpacked_in [7:0],
^~~~~~~~~~~
input unpacked_in [7:0],
^~~~~~~~~~~
... See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Command Failed

6
test_regress/t/t_prot_lib_unpacked_bad.v
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@ -3,10 +3,10 @@
// without warranty, 2019 by Todd Strader.
module secret_impl (
input unpacked_in [7:0],
output unpacked_out [7:0]);
input unpacked_in [7:0],
output unpacked_out [7:0]);
genvar i;
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin
assign unpacked_out[i] = unpacked_in[i];