forked from github/verilator
148 lines
4.4 KiB
Systemverilog
148 lines
4.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Todd Strader.
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`define DRIVE(sig) \
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/* Just throw a bunch of bits at the input */ \
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/* verilator lint_off WIDTH */ \
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sig``_in <= {8{crc}}; \
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/* verilator lint_on WIDTH */
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`define CHECK(sig) \
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if (cyc > 0 && sig``_in != sig``_out) begin \
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$display(`"%%Error (%m) sig``_in (0x%0x) != sig``_out (0x%0x)`", \
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sig``_in, sig``_out); \
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$stop; \
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end
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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localparam last_cyc =
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`ifdef TEST_BENCHMARK
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`TEST_BENCHMARK;
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`else
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10;
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`endif
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genvar x;
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generate
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for (x = 0; x < 2; x = x + 1) begin: gen_loop
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integer cyc = 0;
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reg [63:0] crc = 64'h5aef0c8d_d70a4497;
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logic [31:0] accum_in;
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logic [31:0] accum_out;
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logic accum_bypass;
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logic [31:0] accum_bypass_out;
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logic [31:0] accum_out_expect;
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logic [31:0] accum_bypass_out_expect;
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logic s1_in;
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logic s1_out;
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logic [1:0] s2_in;
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logic [1:0] s2_out;
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logic [7:0] s8_in;
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logic [7:0] s8_out;
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logic [32:0] s33_in;
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logic [32:0] s33_out;
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logic [63:0] s64_in;
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logic [63:0] s64_out;
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logic [64:0] s65_in;
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logic [64:0] s65_out;
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logic [128:0] s129_in;
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logic [128:0] s129_out;
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logic [3:0] [31:0] s4x32_in;
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logic [3:0] [31:0] s4x32_out;
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secret
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secret (
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.accum_in,
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.accum_out,
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.accum_bypass,
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.accum_bypass_out,
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.s1_in,
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.s1_out,
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.s2_in,
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.s2_out,
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.s8_in,
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.s8_out,
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.s33_in,
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.s33_out,
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.s64_in,
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.s64_out,
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.s65_in,
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.s65_out,
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.s129_in,
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.s129_out,
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.s4x32_in,
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.s4x32_out,
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.clk);
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$display("[%0t] x=%0d, cyc=%0d accum_in=%0d accum_out=%0d accum_bypass_out=%0d",
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$time, x, cyc, accum_in, accum_out, accum_bypass_out);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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accum_in <= accum_in + 5;
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// 7 is the secret_value inside the secret module
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accum_out_expect <= accum_in + accum_out_expect + 7;
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`DRIVE(s1)
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`DRIVE(s2)
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`DRIVE(s8)
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`DRIVE(s33)
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`DRIVE(s64)
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`DRIVE(s65)
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`DRIVE(s129)
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`DRIVE(s4x32)
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if (cyc == 0) begin
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accum_in <= x*100;
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accum_bypass <= '0;
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end else if (cyc > 0) begin
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if (accum_out_expect != accum_out) begin
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$display("%%Error: (%m) accum_out expected %0d got %0d",
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accum_out_expect, accum_out);
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$stop;
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end
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if (accum_bypass_out_expect != accum_bypass_out) begin
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$display("%%Error: (%m) accum_bypass_out expected %0d got %0d",
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accum_bypass_out_expect, accum_bypass_out);
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$stop;
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end
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end
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if (cyc == 5) accum_bypass <= '1;
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if (x == 0 && cyc == last_cyc) begin
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$display("final cycle = %0d", cyc);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always @(*) begin
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// XSim (and maybe all event simulators?) sees the moment where
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// s1_in has not yet propagated to s1_out, however, they do always
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// both change at the same time
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/* verilator lint_off STMTDLY */
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#1;
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/* verilator lint_on STMTDLY */
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`CHECK(s1)
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`CHECK(s2)
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`CHECK(s8)
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`CHECK(s33)
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`CHECK(s64)
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`CHECK(s65)
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`CHECK(s129)
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`CHECK(s4x32)
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end
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assign accum_bypass_out_expect = accum_bypass ? accum_in :
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accum_out_expect;
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end
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endgenerate
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endmodule
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