forked from github/verilator
35 lines
2.3 KiB
Plaintext
35 lines
2.3 KiB
Plaintext
%Warning-WIDTH: t/t_lint_width_bad.v:16: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.
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: ... In instance t
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localparam [3:0] XS = 'hx;
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^~
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... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
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%Warning-WIDTH: t/t_lint_width_bad.v:38: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
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: ... In instance t.p4
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wire [4:0] out = in;
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^
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%Warning-WIDTH: t/t_lint_width_bad.v:20: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits.
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: ... In instance t
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wire [4:0] d = (1'b1 << 2) + 5'b1;
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^~
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%Warning-WIDTH: t/t_lint_width_bad.v:26: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits.
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: ... In instance t
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wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter);
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^
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%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits.
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: ... In instance t
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wire [2:0] cnt = (one + one + one + one);
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^
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%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits.
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: ... In instance t
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wire [2:0] cnt = (one + one + one + one);
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^
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%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits.
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: ... In instance t
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wire [2:0] cnt = (one + one + one + one);
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^
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%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits.
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: ... In instance t
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wire [2:0] cnt = (one + one + one + one);
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^
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%Error: Exiting due to
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