forked from github/verilator
9 lines
480 B
Plaintext
9 lines
480 B
Plaintext
%Warning-COMBDLY: t/t_lint_latch_bad.v:24: Delayed assignments (<=) in non-clocked (non flop or latch) block
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: ... Suggest blocking assignments (=)
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bc <= a;
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^~
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... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.
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*** See the manual before disabling this,
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else you may end up with different sim results.
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%Error: Exiting due to
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