forked from github/verilator
33 lines
563 B
Systemverilog
33 lines
563 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic oe;
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read r (.clk(clk), .data( ( ( oe == 1'd001 ) && implicit_write ) ) );
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sets s (.clk(clk), .enable(implicit_write));
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read u (.clk(clk), .data(~implicit_also));
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endmodule
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module sets (
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input clk,
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output enable
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);
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assign enable = 1'b0;
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endmodule
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module read (
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input clk,
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input data
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);
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endmodule
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