forked from github/verilator
33 lines
537 B
Systemverilog
33 lines
537 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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module t (/*AUTOARG*/);
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counter_if iface();
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source source (
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.itf (iface)
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);
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endmodule
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interface counter_if;
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logic [3:0] value;
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endinterface
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module source
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(
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counter_if itf
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);
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logic [3:0] getter;
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initial begin
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getter = itf; // Intended to write itf.value
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getter = 4'd3 + itf; // Intended to write itf.value
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end
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endmodule
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