forked from github/verilator
8 lines
205 B
Systemverilog
8 lines
205 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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int a = -12'd1;
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int b = 1231232312312312'd1;
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