verilator/test_regress/t/t_fuzz_negwidth_bad.v
2019-09-30 19:48:01 -04:00

8 lines
205 B
Systemverilog

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.
int a = -12'd1;
int b = 1231232312312312'd1;