forked from github/verilator
37 lines
564 B
Systemverilog
37 lines
564 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by Todd Strader.
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module c9
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#(parameter A = 1,
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parameter B = 1);
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localparam BITS = A*B;
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localparam SOMEP = {BITS{1'b0}};
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endmodule
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module b9
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#(parameter A = 1);
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c9
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#(.A (A),
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.B (9))
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c9;
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endmodule
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module t;
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b9 b9;
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b9 #(.A (100)) b900;
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b9 #(.A (1000)) b9k;
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initial begin
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// Should never get here
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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