forked from github/verilator
14 lines
301 B
Systemverilog
14 lines
301 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Wilson Snyder.
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module t (b);
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output reg [31:0] b;
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initial begin
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b = 22;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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