Add --stats-vars, bug851.

Changes

@@ -21,6 +21,8 @@ indicates the contributor was also the author of the fix; Thanks!
       Note that SystemC traces will no longer show the signals
       in the wrapper, they can be seen one level further down.
 
+****  Add --stats-vars, bug851. [Jeremy Bennett]
+
 ****  Fix bare generates in interfaces, bug789. [Bob Newgard]
 
 ****  Fix underscores in real literals, bug863. [Jonathon Donaldson]

bin/verilator

@@ -309,6 +309,7 @@ descriptions in the next sections for more information.
     --savable			Enable model save-restore
     --sc                        Create SystemC output
     --stats                     Create statistics file
+    --stats-vars                Provide statistics on variables
      -sv                        Enable SystemVerilog parsing
      +systemverilogext+<ext>    Synonym for +1800-2012ext+<ext>
     --top-module <topname>      Name of top level input module
@@ -966,6 +967,12 @@ Specifies SystemC output mode; see also --cc.
 
 Creates a dump file with statistics on the design in {prefix}__stats.txt.
 
+=item --stats-vars
+
+Creates more detailed statistics including a list of all the variables by
+size (plain --stats just gives a count).  See --stats, which is implied by
+this.
+
 =item -sv
 
 Specifies SystemVerilog language features should be enabled; equivalent to

src/V3Options.cpp

@@ -761,6 +761,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
 	    else if ( onoff   (sw, "-skip-identical", flag/*ref*/) )	{ m_skipIdentical = flag; }
 	    else if ( !strcmp (sw, "-sp-deprecated") )			{ m_outFormatOk = true; m_systemC = true; m_systemPerl = true; } // Undocumented, old
 	    else if ( onoff   (sw, "-stats", flag/*ref*/) )		{ m_stats = flag; }
+	    else if ( onoff   (sw, "-stats-vars", flag/*ref*/) )	{ m_statsVars = flag; m_stats |= flag; }
 	    else if ( !strcmp (sw, "-sv") )				{ m_defaultLanguage = V3LangCode::L1800_2005; }
 	    else if ( onoff   (sw, "-trace", flag/*ref*/) )		{ m_trace = flag; }
 	    else if ( onoff   (sw, "-trace-dups", flag/*ref*/) )	{ m_traceDups = flag; }
@@ -1228,6 +1229,7 @@ V3Options::V3Options() {
     m_savable = false;
     m_skipIdentical = true;
     m_stats = false;
+    m_statsVars = false;
     m_systemC = false;
     m_systemPerl = false;
     m_trace = false;

src/V3Options.h

@@ -87,6 +87,7 @@ class V3Options {
     bool	m_skipIdentical;// main switch: --skip-identical
     bool	m_systemPerl;	// main switch: --sp: System Perl instead of SystemC (m_systemC also set)
     bool	m_stats;	// main switch: --stats
+    bool	m_statsVars;	// main switch: --stats-vars
     bool	m_trace;	// main switch: --trace
     bool	m_traceDups;	// main switch: --trace-dups
     bool	m_traceParams;	// main switch: --trace-params
@@ -202,6 +203,7 @@ class V3Options {
     bool savable() const { return m_savable; }
     bool skipIdentical() const { return m_skipIdentical; }
     bool stats() const { return m_stats; }
+    bool statsVars() const { return m_statsVars; }
     bool assertOn() const { return m_assert; }  // assertOn as __FILE__ may be defined
     bool autoflush() const { return m_autoflush; }
     bool bboxSys() const { return m_bboxSys; }

src/V3Stats.cpp

@@ -40,6 +40,9 @@
 class StatsVisitor : public AstNVisitor {
 private:
     // NODE STATE/TYPES
+
+    typedef map<string,int>	NameMap;	// Number of times a name appears
+
     // STATE
     string	m_stage;		// Name of the stage we are scanning
     bool	m_fast;			// Counting only fastpath
@@ -54,7 +57,8 @@ private:
     V3Double0		m_statPred[AstBranchPred::_ENUM_END];	// Nodes of given type
     V3Double0		m_statInstr;		// Instruction count
     V3Double0		m_statInstrFast;	// Instruction count
-    vector<V3Double0>	m_statVarWidths;	// Variables of given type
+    vector<V3Double0>	m_statVarWidths;	// Variables of given width
+    vector<NameMap>	m_statVarWidthNames;	// Var names of given width
     V3Double0		m_statVarArray;		// Statistic tracking
     V3Double0		m_statVarBytes;		// Statistic tracking
     V3Double0		m_statVarClock;		// Statistic tracking
@@ -100,8 +104,18 @@ private:
 	    else m_statVarBytes += nodep->dtypeSkipRefp()->widthTotalBytes();
 	    if (int(m_statVarWidths.size()) <= nodep->width()) {
 		m_statVarWidths.resize(nodep->width()+5);
+		if (v3Global.opt.statsVars()) m_statVarWidthNames.resize(nodep->width()+5);
 	    }
 	    ++ m_statVarWidths.at(nodep->width());
+	    string pn = nodep->prettyName();
+	    if (v3Global.opt.statsVars()) {
+		NameMap& nameMapr = m_statVarWidthNames.at(nodep->width());
+		if (nameMapr.find(pn) != nameMapr.end()) {
+		    nameMapr[pn]++;
+		} else {
+		    nameMapr[pn]=1;
+		}
+	    }
 	}
     }
     virtual void visit(AstVarScope* nodep, AstNUser*) {
@@ -208,8 +222,16 @@ public:
 	}
 	for (unsigned i=0; i<m_statVarWidths.size(); i++) {
 	    if (double count = double(m_statVarWidths.at(i))) {
-		ostringstream os; os<<"Vars, width "<<setw(4)<<dec<<i;
-		V3Stats::addStat(m_stage, os.str(), count);
+		if (v3Global.opt.statsVars()) {
+		    NameMap& nameMapr = m_statVarWidthNames.at(i);
+		    for (NameMap::iterator it=nameMapr.begin(); it!=nameMapr.end(); ++it) {
+			ostringstream os; os<<"Vars, width "<<setw(5)<<dec<<i<<" "<<it->first;
+			V3Stats::addStat(m_stage, os.str(), it->second);
+		    }
+		} else {
+		    ostringstream os; os<<"Vars, width "<<setw(5)<<dec<<i;
+		    V3Stats::addStat(m_stage, os.str(), count);
+		}
 	    }
 	}
 	// Node types

test_regress/t/t_flag_stats.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+compile (
+    verilator_flags2 => ["--stats --stats-vars"],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_flag_stats.v

@@ -0,0 +1,13 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+module t (b);
+   output reg [31:0] b;
+   initial begin
+      b = 22;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule