forked from github/verilator
61 lines
1.2 KiB
Systemverilog
61 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2016 by Geoff Barrett.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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// verilator lint_off LITENDIAN
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logic arrd [0:1] = '{ 1'b1, 1'b0 };
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// verilator lint_on LITENDIAN
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logic y0, y1;
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logic localbkw [1:0];
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arr_rev arr_rev_u (
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.arrbkw (arrd),
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.y0(y0),
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.y1(y1)
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);
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always @ (posedge clk) begin
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if (arrd[0] != 1'b1) $stop;
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if (arrd[1] != 1'b0) $stop;
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localbkw = arrd;
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`ifdef TEST_VERBOSE
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$write("localbkw[0]=%b\n", localbkw[0]);
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$write("localbkw[1]=%b\n", localbkw[1]);
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`endif
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if (localbkw[0] != 1'b0) $stop;
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if (localbkw[1] != 1'b1) $stop;
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`ifdef TEST_VERBOSE
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$write("y0=%b\n", y0);
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$write("y1=%b\n", y1);
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`endif
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if (y0 != 1'b0) $stop;
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if (y1 != 1'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module arr_rev
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(
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input var logic arrbkw [1:0],
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output var logic y0,
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output var logic y1
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);
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always_comb y0 = arrbkw[0];
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always_comb y1 = arrbkw[1];
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endmodule
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