forked from github/verilator
Fix slicing mix of big and little-endian, bug1033.
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@ -21,6 +21,8 @@ indicates the contributor was also the author of the fix; Thanks!
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**** Fix crash on very deep function trees, bug1028. [Jonathan Kimmitt]
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**** Fix slicing mix of big and little-endian, bug1033. [Geoff Barrett]
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* Verilator 3.880 2015-12-19
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@ -412,10 +412,10 @@ public:
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AstVar* pinVarp = pinp->modVarp();
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AstVarRef* connectRefp = pinp->exprp()->castVarRef();
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AstVarXRef* connectXRefp = pinp->exprp()->castVarXRef();
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AstBasicDType* pinBasicp = pinVarp->dtypep()->basicp(); // Maybe NULL
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AstBasicDType* pinBasicp = pinVarp->dtypep()->castBasicDType(); // Maybe NULL
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AstBasicDType* connBasicp = NULL;
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AstAssignW* assignp = NULL;
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if (connectRefp) connBasicp = connectRefp->varp()->dtypep()->basicp();
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if (connectRefp) connBasicp = connectRefp->varp()->dtypep()->castBasicDType();
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//
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if (!alwaysCvt
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&& connectRefp
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@ -102,6 +102,9 @@ class SliceCloneVisitor : public AstNVisitor {
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AstUnpackArrayDType* adtypep = nodep->fromp()->dtypep()->skipRefp()->castUnpackArrayDType();
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if (!adtypep) nodep->v3fatalSrc("slice select tried to expand an array without an ArrayDType");
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unsigned idx = nodep->start() + m_selBits[m_vecIdx][m_depth] - adtypep->lsb();
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if (adtypep->rangep()->littleEndian()) { // Little must iterate backwards
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idx = adtypep->rangep()->elementsConst() - 1 - idx;
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}
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AstNode* constp = new AstConst(bitp->fileline(), V3Number(bitp->fileline(), bitp->castConst()->num().width(), idx));
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bitp->replaceWith(constp);
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} else {
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@ -255,15 +258,15 @@ class SliceVisitor : public AstNVisitor {
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return clones;
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}
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AstArraySel* insertImplicit(AstNode* nodep, unsigned start, unsigned count) {
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AstArraySel* insertImplicit(AstNode* nodep, unsigned startDim, unsigned numDimensions) {
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// Insert any implicit slices as explicit slices (ArraySel nodes).
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// Return a new pointer to replace nodep() in the ArraySel.
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UINFO(9," insertImplicit (start="<<start<<",c="<<count<<") "<<nodep<<endl);
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UINFO(9," insertImplicit (startDim="<<startDim<<",c="<<numDimensions<<") "<<nodep<<endl);
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AstVarRef* refp = nodep->user1p()->castNode()->castVarRef();
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if (!refp) nodep->v3fatalSrc("No VarRef in user1 of node "<<nodep);
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AstVar* varp = refp->varp();
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AstNode* topp = nodep;
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for (unsigned i = start; i < start + count; ++i) {
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for (unsigned i = startDim; i < startDim + numDimensions; ++i) {
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AstNodeDType* dtypep = varp->dtypep()->dtypeDimensionp(i-1);
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AstUnpackArrayDType* adtypep = dtypep->castUnpackArrayDType();
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if (!adtypep) nodep->v3fatalSrc("insertImplicit tried to expand an array without an ArrayDType");
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18
test_regress/t/t_array_rev.pl
Executable file
18
test_regress/t/t_array_rev.pl
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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60
test_regress/t/t_array_rev.v
Normal file
60
test_regress/t/t_array_rev.v
Normal file
@ -0,0 +1,60 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2016 by Geoff Barrett.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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// verilator lint_off LITENDIAN
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logic arrd [0:1] = '{ 1'b1, 1'b0 };
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// verilator lint_on LITENDIAN
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logic y0, y1;
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logic localbkw [1:0];
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arr_rev arr_rev_u (
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.arrbkw (arrd),
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.y0(y0),
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.y1(y1)
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);
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always @ (posedge clk) begin
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if (arrd[0] != 1'b1) $stop;
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if (arrd[1] != 1'b0) $stop;
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localbkw = arrd;
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`ifdef TEST_VERBOSE
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$write("localbkw[0]=%b\n", localbkw[0]);
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$write("localbkw[1]=%b\n", localbkw[1]);
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`endif
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if (localbkw[0] != 1'b0) $stop;
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if (localbkw[1] != 1'b1) $stop;
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`ifdef TEST_VERBOSE
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$write("y0=%b\n", y0);
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$write("y1=%b\n", y1);
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`endif
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if (y0 != 1'b0) $stop;
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if (y1 != 1'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module arr_rev
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(
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input var logic arrbkw [1:0],
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output var logic y0,
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output var logic y1
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);
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always_comb y0 = arrbkw[0];
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always_comb y1 = arrbkw[1];
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endmodule
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@ -8,12 +8,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
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# Version 2.0.
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compile (
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verilator_flags2 => ["--lint-only"],
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fails=>1,
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expect=>
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q{%Error: t/t_inst_misarray_bad.v:\d+: Illegal assignment of constant to unpacked array
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%Error: Exiting due to.*},
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);
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verilator_flags2 => ["--lint-only"],
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fails=>0,
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verilator_make_gcc => 0,
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make_top_shell => 0,
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make_main => 0,
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# Once got illegal assignment, but new slicing rules don't always detect this.
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# Due to V3Width.cpp pinwidth != conwidth requirement on data type mismatches
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);
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ok(1);
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@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
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# Version 2.0.
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compile (
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v_flags2 => ["--lint-only"],
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verilator_flags2 => ["--lint-only"],
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fails=>0,
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verilator_make_gcc => 0,
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make_top_shell => 0,
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