forked from github/verilator
11 lines
291 B
Plaintext
11 lines
291 B
Plaintext
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Stefan Wallentowitz.
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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clocker -module "t" -var "clk*"
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no_clocker -module "t" -var "data_in"
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