forked from github/verilator
6 lines
264 B
Plaintext
6 lines
264 B
Plaintext
%Error-WIDTH: t/t_flag_werror.v:9:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
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: ... In instance t
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wire [3:0] foo = 6'h2e;
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^
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%Error: Exiting due to
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