forked from github/verilator
9 lines
215 B
Systemverilog
9 lines
215 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
|
// without warranty, 2019 by Wilson Snyder.
|
|
|
|
module t (portwithoin);
|
|
input portwithin;
|
|
endmodule
|